BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation
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Maxime Nassar, Shivam Bhasin, Jean-Luc Danger, Guillaume Duc, Sylvain Guilley
BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation
DATE, 2010.

DATE 2010
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@inproceedings{DATE-2010-NassarBDDG,
	author        = "Maxime Nassar and Shivam Bhasin and Jean-Luc Danger and Guillaume Duc and Sylvain Guilley",
	booktitle     = "{Proceedings of the 14th Conference on Design, Automation and Test in Europe}",
	pages         = "849--854",
	publisher     = "{IEEE}",
	title         = "{BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation}",
	year          = 2010,
}

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