Di Chen, Hai Jin 0001, Xiaofei Liao, Haikun Liu, Rentong Guo, Dong Liu
MALRU: Miss-penalty aware LRU-based cache replacement for hybrid memory systems
DATE, 2017.
@inproceedings{DATE-2017-ChenJLLGL,
author = "Di Chen and Hai Jin 0001 and Xiaofei Liao and Haikun Liu and Rentong Guo and Dong Liu",
booktitle = "{Proceedings of the 21st Conference and Exhibition on Design, Automation and Test in Europe}",
doi = "10.23919/DATE.2017.7927151",
isbn = "978-3-9815370-8-6",
pages = "1086--1091",
publisher = "{IEEE}",
title = "{MALRU: Miss-penalty aware LRU-based cache replacement for hybrid memory systems}",
year = 2017,
}