BibSLEIGH — Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation

Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay
Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation
DATE, 2017.

DATE 2017

@inproceedings{DATE-2017-NaKM,
	author        = "Taesik Na and Jong Hwan Ko and Saibal Mukhopadhyay",
	booktitle     = "{Proceedings of the 21st Conference and Exhibition on Design, Automation and Test in Europe}",
	doi           = "10.23919/DATE.2017.7927229",
	isbn          = "978-3-9815370-8-6",
	pages         = "1504--1509",
	publisher     = "{IEEE}",
	title         = "{Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation}",
	year          = 2017,
}

Taesik Na, Jong Hwan Ko, Saibal MukhopadhyayClock data compensation aware clock tree synthesis in digital circuits with adaptive clock generationDATE, 2017.

Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay
Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation
DATE, 2017.