An 830mW, 586kbps 1024-bit RSA chip design
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Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang
An 830mW, 586kbps 1024-bit RSA chip design
DATE, 2006.

DATE DF 2006
Full names Links ISxN
	author        = "Chingwei Yeh and En-Feng Hsu and Kai-Wen Cheng and Jinn-Shyan Wang and Nai-Jen Chang",
	booktitle     = "{Proceedings of the 10th Conference on Design, Automation and Test in Europe: Designers’ Forum}",
	doi           = "10.1145/1131355.1131361",
	isbn          = "3-9810801-0-6",
	pages         = "24--29",
	publisher     = "{European Design and Automation Association, Leuven, Belgium}",
	title         = "{An 830mW, 586kbps 1024-bit RSA chip design}",
	year          = 2006,


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