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Travelled to:
1 × Canada
1 × Germany
Collaborated with:
C.M.Lott M.Ü.Uyar P.D.Amer A.Y.Duale Y.Wang S.S.Batth A.Wise
Talks about:
timer (2) clearinghous (1) electron (1) conflict (1) process (1) presenc (1) multipl (1) generat (1) system (1) requir (1)

Person: Mariusz A. Fecko

DBLP DBLP: Fecko:Mariusz_A=

Facilitated 1 volumes:

TestCom 2006Ed

Contributed to:

TestCom 20052005
RE 20022002
TestCom 20002000

Wrote 3 papers:

TestCom-2005-UyarWBWF #fault #modelling #multi
Timing Fault Models for Systems with Multiple Timers (MÜU, YW, SSB, AW, MAF), pp. 192–208.
RE-2002-FeckoL #process #requirements
Improving the Requirements Engineering Process for an Electronic Clearinghouse (MAF, CML), pp. 52–60.
TestCom-2000-FeckoAUD #generative #testing
Test Generation in the Presence of Conflicting Timers (MAF, PDA, MÜU, AYD), p. 301–?.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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