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Travelled to:
1 × Germany
Collaborated with:
P.Fradet A.Girault
Talks about:
modular (1) circuit (1) redund (1) voter (1) verif (1) tripl (1) minim (1) guid (1)

Person: Dmitry Burlyaev

DBLP DBLP: Burlyaev:Dmitry

Contributed to:

DATE 20142014

Wrote 1 papers:

DATE-2014-BurlyaevFG
Verification-guided voter minimization in triple-modular redundant circuits (DB, PF, AG), pp. 1–6.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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