At-Speed Logic BIST for IP Cores
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B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu
At-Speed Logic BIST for IP Cores
DATE, 2005.

DATE 2005
Full names Links ISxN
	author        = "B. Cheon and E. Lee and Laung-Terng Wang and Xiaoqing Wen and P. Hsu and J. Cho and J. Park and H. Chao and Shianling Wu",
	booktitle     = "{Proceedings of the Ninth Conference on Design, Automation and Test in Europe}",
	doi           = "10.1109/DATE.2005.70",
	isbn          = "0-7695-2288-2",
	pages         = "860--861",
	publisher     = "{IEEE Computer Society}",
	title         = "{At-Speed Logic BIST for IP Cores}",
	year          = 2005,


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