BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Used together with:
test (27)
base (14)
scan (12)
logic (10)
use (8)

Stem bist$ (all stems)

70 papers:

DACDAC-2014-ReimannGTCGUWEA #architecture #integration
Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures (FR, MG, JT, AC, LRG, DU, HJW, PE, UA), p. 9.
DATEDATE-2014-DogaruSR #flexibility
A flexible BIST strategy for SDR transmitters (ED, FVdS, WR), pp. 1–6.
DATEDATE-2014-KahngK #logic #memory management #scheduling
Co-optimization of memory BIST grouping, test scheduling, and logic placement (ABK, IK), pp. 1–6.
DATEDATE-2014-MaliukM #framework #network #prototype
An analog non-volatile neural network platform for prototyping RF BIST solutions (DM, YM), pp. 1–6.
DATEDATE-2012-Voyiatzis #concurrent #logic #monitoring #multi
Input vector monitoring on line concurrent BIST based on multilevel decoding logic (IV), pp. 1251–1256.
DATEDATE-2008-AsianVR #implementation #network
Practical Implementation of a Network Analyzer for Analog BIST Applications (MJBA, DV, AR), pp. 80–85.
DATEDATE-2008-StratigopoulosTM #estimation #parametricity
A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation (HGDS, JT, SM), pp. 68–73.
DATEDATE-2008-VenutoR #generative
PWM-Based Test Stimuli Generation for BIST of High Resolution ADCs (DDV, LR), pp. 284–287.
DATEDATE-2007-ZjajoAG #interactive #monitoring #parametricity #process
Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits (AZ, MJBA, JPdG), pp. 1301–1306.
DATEDATE-2006-DhayniMRB #functional #linear #pseudo
Pseudorandom functional BIST for linear and nonlinear MEMS (AD, SM, LR, AB), pp. 664–669.
DATEDATE-2005-CheonLWWHCPCW #logic
At-Speed Logic BIST for IP Cores (BC, EL, LTW, XW, PH, JC, JP, HC, SW), pp. 860–861.
DATEDATE-2005-LiC #analysis #clustering #hybrid #sequence
Hybrid BIST Based on Repeating Sequences and Cluster Analysis (LL, KC), pp. 1142–1147.
DATEDATE-2005-NegreirosCS #evaluation #low cost #using
Noise Figure Evaluation Using Low Cost BIST (MN, LC, AAS), pp. 158–163.
DACDAC-2004-Pomeranz04a
Scan-BIST based on transition probabilities (IP), pp. 940–943.
DACDAC-2004-WohlWP #architecture #scalability
Scalable selector architecture for x-tolerant deterministic BIST (PW, JAW, SP), pp. 934–939.
DATEDATE-2005-BernardiMQR04 #approach #logic #testing #using
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study (PB, GM, FQ, MSR), pp. 228–233.
DACDAC-2003-LiYRP #generative #markov #using
A scan BIST generation method using a markov source and partial bit-fixing (WL, CY, SMR, IP), pp. 554–559.
DACDAC-2003-NegreirosCS #low cost
Ultimate low cost analog BIST (MN, LC, AAS), pp. 570–573.
DACDAC-2003-WohlWPA #architecture #logic #performance
Efficient compression and application of deterministic patterns in a logic BIST architecture (PW, JAW, SP, MBA), pp. 566–569.
DATEDATE-2003-BernardiRRV #approach #embedded #programmable
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories (PB, MR, MSR, MV), pp. 10720–10725.
DATEDATE-2003-LiuC #approach #fault #identification
A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis (CL, KC), pp. 10230–10237.
DATEDATE-2003-LupeaPJ #analysis #named
RF-BIST: Loopback Spectral Signature Analysis (DL, UP, HJJ), pp. 10478–10483.
DATEDATE-2003-PolianBR #markov #optimisation #pseudo #random
Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST (IP, BB, SMR), pp. 11184–11185.
DATEDATE-2003-SantosFTT #generative #quality
RTL Test Pattern Generation for High Quality Loosely Deterministic BIST (MBS, JMF, ICT, JPT), pp. 10994–10999.
DACDAC-2002-WohlWPM #effectiveness
Effective diagnostics through interval unloads in a BIST environment (PW, JAW, SP, GAM), pp. 249–254.
DATEDATE-2002-BayraktarogluO #fault
Gate Level Fault Diagnosis in Scan-Based BIST (IB, AO), pp. 376–381.
DATEDATE-2002-Hoffmann #design #generative #testing
A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits (CH), pp. 197–204.
DATEDATE-2002-KapurWM #logic
Directed-Binary Search in Logic BIST Diagnostics (RK, TWW, MRM), p. 1121.
DATEDATE-2002-LiuCG #identification
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment (CL, KC, MG), pp. 382–386.
DACDAC-2001-OckunzziP #algorithm
Test Strategies for BIST at the Algorithmic and Register-Transfer Levels (KAO, CAP), pp. 65–70.
DATEDATE-2001-AzaisBBR #implementation #linear
Implementation of a linear histogram BIST for ADCs (FA, SB, YB, MR), pp. 590–595.
DATEDATE-2001-BayraktarogluO
Diagnosis for scan-based BIST: reaching deep into the signatures (IB, AO), pp. 102–111.
DATEDATE-2001-IrionKVW #clustering #logic #performance #synthesis
Circuit partitioning for efficient logic BIST synthesis (AI, GK, HPEV, HJW), pp. 86–91.
DATEDATE-2001-NicoliciA #3d #design #testing #trade-off
Testability trade-offs for BIST RTL data paths: the case for three dimensional design space (NN, BMAH), p. 802.
SACSAC-2001-CornoRS #architecture #effectiveness #evolution
Evolving effective CA/CSTP: BIST architectures for sequential circuits (FC, MSR, GS), pp. 345–350.
DACDAC-2000-BayraktarogluO #fault
Improved fault diagnosis in scan-based BIST via superposition (IB, AO), pp. 55–58.
DATEDATE-2000-BergfeldNR #embedded #testing #using
Diagnostic Testing of Embedded Memories Using BIST (TJB, DN, EMR), pp. 305–309.
DATEDATE-2000-CataldoCPW #functional #generative #hardware
Optimal Hardware Pattern Generation for Functional BIST (SC, SC, PP, HJW), pp. 292–297.
DATEDATE-2000-CotaRABCL #reuse
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte (ÉFC, MR, FA, YB, LC, ML), pp. 226–230.
DATEDATE-2000-GizopoulosKPPZ #effectiveness #power management
Effective Low Power BIST for Datapaths (DG, NK, MP, AMP, YZ), p. 757.
DATEDATE-2000-GoodbyO #fault #quality
Test Quality and Fault Risk in Digital Filter Datapath BIST (LG, AO), pp. 468–475.
DATEDATE-2000-HuangOC #testing
A BIST Scheme for On-Chip ADC and DAC Testing (JLH, CKO, KTC), pp. 216–220.
DATEDATE-2000-LuW #logic #memory management #modelling
Cost and Benefit Models for Logic and Memory BIST (JML, CWW), pp. 710–714.
DATEDATE-2000-SilvaDM #configuration management #correlation #hardware #using
Mixed-Signal BIST Using Correlation and Reconfigurable Hardware (JMdS, JSD, JSM), p. 744.
DATEDATE-2000-SugiharaYD #analysis #approach
Analysis and Minimization of Test Time in a Combined BIST and External Test Approach (MS, HY, HD), pp. 134–140.
DACDAC-1999-TsaiCB #quality #using
Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme (HCT, KTC, SB), pp. 748–753.
DATEDATE-1999-HellebrandWY #symmetry
Symmetric Transparent BIST for RAMs (SH, HJW, VNY), pp. 702–707.
DATEDATE-1999-NicoliciA #hardware #performance
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths (NN, BMAH), p. 289–?.
DATEDATE-1999-PaschalisKPGZ #architecture #effectiveness #multi #performance
An Effective BIST Architecture for Fast Multiplier Cores (AMP, NK, MP, DG, YZ), pp. 117–121.
DATEDATE-1999-RayaneVN #detection #embedded
A One-Bit-Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection (IR, JVM, MN), p. 792–?.
DACDAC-1998-GhoshJB #analysis #testing
A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis (IG, NKJ, SB), pp. 554–559.
DACDAC-1998-ParulkarGB #behaviour
Introducing Redundant Computations in a Behavior for Reducing BIST Resources (IP, SKG, MAB), pp. 548–553.
DATEDATE-1998-ParulkarGB #scheduling
Scheduling and Module Assignment for Reducing Bist Resources (IP, SKG, MAB), pp. 66–73.
DATEDATE-1998-YarmolikHW #performance #self
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs (VNY, SH, HJW), pp. 173–179.
DACDAC-1997-GoodbyO
Frequency-Domain Compatibility in Digital Filter BIST (LG, AO), pp. 540–545.
DACDAC-1997-TsaiCLB #algorithm #hybrid
A Hybrid Algorithm for Test Point Selection for Scan-Based BIST (HCT, KTC, CJL, SB), pp. 478–483.
DATEEDTC-1997-Kristof #architecture #bound #effectiveness #idea #self #testing
Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections (AK), p. 630.
DATEEDTC-1997-NouraniP #analysis #behaviour #using
Structural BIST insertion using behavioral test analysis (MN, CAP), pp. 64–68.
DACDAC-1995-ParulkarGB #design
Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead (IP, SKG, MAB), pp. 395–401.
DACDAC-1994-ParulkarBN #representation
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST (IP, MAB, CN), pp. 345–356.
DATEEDAC-1994-ChenG #generative #testing
BIST Test Pattern Generators for Stuck-Open and Delay Testing (CAC, SKG), pp. 289–296.
DATEEDAC-1994-HarrisO #concurrent #fine-grained #scheduling
Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST (IGH, AO), pp. 119–123.
DATEEDAC-1994-IllmanT #architecture
A Fragmented Register Architecture and Test Advisor for BIST (RI, DJT), pp. 124–129.
DATEEDAC-1994-LinGB #generative #low cost #novel
A Low Cost BIST Methodology and Associated Novel Test Pattern Generator (SPL, SKG, MAB), pp. 106–112.
DATEEDAC-1994-VuksicF #approach #fault #testing
A New BIST Approach for Delay Fault Testing (AV, KF), pp. 284–288.
DACDAC-1990-UpadhyayaT #case study
BIST PLAs, Pass or Fail — A Case Study (SJU, JAT), pp. 724–727.
DACDAC-1988-KimTH #automation #hardware #using
Automatic Insertion of BIST Hardware Using VHDL (KK, JGT, DSH), pp. 9–15.
DACDAC-1988-Stroud #approach #automation #logic #synthesis
An Automated BIST Approach for General Sequential Logic Synthesis (CES), pp. 3–8.
DACDAC-1987-KrasniewskiP #low cost #self
Circular Self-Test Path: A Low-Cost BIST Technique (AK, SP), pp. 407–415.
DACDAC-1987-LiuSU #array #design #logic #named #programmable #scalability #self
BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays (CYL, KKS, SJU), pp. 385–391.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.