BibSLEIGH — Checking and deriving module paths in Verilog cell library descriptions

Matthias Raffelsieper, Mohammad Reza Mousavi, Chris W. H. Strolenberg
Checking and deriving module paths in Verilog cell library descriptions
DATE, 2010.

DATE 2010

@inproceedings{DATE-2010-RaffelsieperMS,
	author        = "Matthias Raffelsieper and Mohammad Reza Mousavi and Chris W. H. Strolenberg",
	booktitle     = "{Proceedings of the 14th Conference on Design, Automation and Test in Europe}",
	pages         = "1506--1511",
	publisher     = "{IEEE}",
	title         = "{Checking and deriving module paths in Verilog cell library descriptions}",
	year          = 2010,
}

Matthias Raffelsieper, Mohammad Reza Mousavi, Chris W. H. StrolenbergChecking and deriving module paths in Verilog cell library descriptionsDATE, 2010.

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Matthias Raffelsieper, Mohammad Reza Mousavi, Chris W. H. Strolenberg
Checking and deriving module paths in Verilog cell library descriptions
DATE, 2010.