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Travelled to:
1 × France
Collaborated with:
R.Kaivola R.Ghughal N.Narasimhan J.Whittemore S.Pandav A.Slobodová C.Taylor V.Frolov E.Reeber A.Naik
Talks about:
processor (1) replac (1) formal (1) execut (1) verif (1) valid (1) intel (1) engin (1) test (1) core (1)

Person: Amber Telfer

DBLP DBLP: Telfer:Amber

Contributed to:

CAV 20092009

Wrote 1 papers:

CAV-2009-KaivolaGNTWPSTFRN #execution #testing #validation #verification
Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation (RK, RG, NN, AT, JW, SP, AS, CT, VF, ER, AN), pp. 414–429.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.