Travelled to:1 × France
1 × USA
Collaborated with:W.A.H.Jr. R.Kaivola R.Ghughal N.Narasimhan A.Telfer J.Whittemore S.Pandav A.Slobodová C.Taylor V.Frolov A.Naik
Talks about:processor (1) subclass (1) procedur (1) formula (1) replac (1) formal (1) execut (1) verif (1) valid (1) unrol (1)
Person: Erik Reeber
DBLP: Reeber:Erik
Contributed to:
2009
2006Wrote 2 papers:
- CAV-2009-KaivolaGNTWPSTFRN #execution #testing #validation #verification
- Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation (RK, RG, NN, AT, JW, SP, AS, CT, VF, ER, AN), pp. 414–429.
- IJCAR-2006-ReeberH #satisfiability #subclass
- A SAT-Based Decision Procedure for the Subclass of Unrollable List Formulas in ACL2 (SULFA) (ER, WAHJ), pp. 453–467.