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Travelled to:
2 × USA
Collaborated with:
C.M.Peters S.A.Szygenda
Talks about:
logic (2) techniqu (1) function (1) stepwis (1) develop (1) pseudo (1) integr (1) simul (1) refin (1) modul (1)

Person: Anthony A. Lekkos

DBLP DBLP: Lekkos:Anthony_A=

Contributed to:

DAC 19781978
DAC 19731973

Wrote 2 papers:

DAC-1978-LekkosP #how #logic #pseudo #refinement #using
How to develop module logic using pseudo-code and stepwise refinement (AAL, CMP), pp. 366–370.
DAC-1973-SzygendaL #functional #logic #simulation
Integrated techniques for functional and gate-level digital logic simulation (SAS, AAL), pp. 159–172.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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