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Travelled to:
1 × Denmark
Collaborated with:
R.Vemuri
Talks about:
transform (1) precondit (1) tempor (1) design (1) verif (1)

Person: Anuradha Sridhar

DBLP DBLP: Sridhar:Anuradha

Contributed to:

CAV 19911991

Wrote 1 papers:

CAV-1991-VemuriS #design #verification
Temporal Precondition Verification of Design Transformations (RV, AS), pp. 125–135.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.