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Travelled to:
1 × Denmark
5 × Germany
7 × France
8 × USA
Collaborated with:
A.Doboli I.Ouaiss S.Govindarajan M.Kaul S.Ganesan A.Núñez-Aldana A.Das M.Ding M.Handa J.Walrath A.Agarwal H.Sampath N.R.Dhanwada A.Pradhan B.Sethuraman H.Yang R.F.Badaoui A.Bhaduri J.Khan V.Yelamanchili S.Ganesan N.Mansouri R.Mandayam J.Roy A.Sridhar H.Xu W.Jone E.Teica R.Radhakrishnan V.Srinivasan S.Radhakrishnan W.Bradley R.Dutta M.Ranjan W.Verhaegen G.G.E.Gielen P.Mamtora P.Sinha N.Kumar R.Vutukuru
Talks about:
analog (18) synthesi (17) design (12) circuit (10) perform (8) system (8) use (8) base (7) reconfigur (6) partit (6)

Person: Ranga Vemuri

DBLP DBLP: Vemuri:Ranga

Contributed to:

DATE 20092009
DAC 20082008
DATE 20082008
DATE 20062006
DAC 20052005
DATE 20052005
DAC 20042004
DATE v1 20042004
DATE v2 20042004
DATE 20022002
DAC 20012001
DATE 20012001
DATE 20002000
DAC 19991999
DATE 19991999
DATE 19981998
DAC 19971997
ED&TC 19971997
DAC 19931993
DAC 19921992
CAV 19911991

Wrote 42 papers:

DATE-2009-DasV #approach #automation #design #grammarware #graph grammar #multi
A graph grammar based approach to automated multi-objective analog circuit design (AD, RV), pp. 700–705.
DATE-2009-XuVJ #runtime
Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage (HX, RV, WBJ), pp. 594–597.
DAC-2008-DasV #adaptation #synthesis
Topology synthesis of analog circuits based on adaptively generated building blocks (AD, RV), pp. 44–49.
DATE-2008-PradhanV #performance #synthesis #using
Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches (AP, RV), pp. 523–526.
DATE-2006-SethuramanV #architecture #automation #generative #multi #named #using
optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs (BS, RV), pp. 947–952.
DATE-2006-YangV #analysis #evaluation #performance #synthesis
Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis (HY, RV), pp. 283–284.
DAC-2005-DingV #megamodelling #performance
A combined feasibility and performance macromodel for analog circuits (MD, RV), pp. 63–68.
DATE-2005-BadaouiV #multi #performance #synthesis
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis (RFB, RV), pp. 138–143.
DATE-2005-BhaduriV #higher-order #induction #metric
Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric (AB, RV), pp. 922–923.
DATE-2005-DingV #approach #megamodelling #modelling #performance
A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling (MD, RV), pp. 1088–1089.
DATE-2005-KhanV #algorithm #scheduling
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms (JK, RV), pp. 622–627.
DAC-2004-AgarwalSYV #modelling #performance
Fast and accurate parasitic capacitance models for layout-aware (AA, HS, VY, RV), pp. 145–150.
DAC-2004-HandaV #algorithm #online #performance
An efficient algorithm for finding empty space for online FPGA placement (MH, RV), pp. 960–965.
DATE-v1-2004-HandaV #algorithm #performance
A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement (MH, RV), pp. 744–745.
DATE-v1-2004-RanjanVASVG #modelling #performance #synthesis #using
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models (MR, WV, AA, HS, RV, GGEG), pp. 604–609.
DATE-v2-2004-AgarwalSYV #estimation
Accurate Estimation of Parasitic Capacitances in Analog Circuits (AA, HS, VY, RV), pp. 1364–1365.
DATE-2002-DoboliV #co-evolution #design #functional #specification
A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems (AD, RV), pp. 760–767.
DAC-2001-DoboliV #constraints #design #synthesis
Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints (AD, RV), pp. 629–634.
DAC-2001-GanesanV #behaviour #clustering #synthesis
Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems (SG, RV), pp. 133–138.
DATE-2001-DoboliV #analysis #network #scalability
A regularity-based hierarchical symbolic analysis method for large-scale analog networks (AD, RV), p. 806.
DATE-2001-OuaissV #configuration management #memory management #synthesis
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers (IO, RV), pp. 650–657.
DATE-2001-TeicaRV #automation #design #on the #using #verification
On the verification of synthesized designs using automatically generated transformational witnesses (ET, RR, RV), p. 798.
DATE-2000-GanesanV #array #programmable
Technology Mapping and Retargeting for Field-Programmable Analog Arrays (SG, RV), pp. 58–64.
DATE-2000-GanesanV00a #clustering #configuration management #design #latency
An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement (SG, RV), pp. 320–325.
DATE-2000-GovindarajanV #quality #scheduling
Improving the Schedule Quality of Static-List Time-Constrained Scheduling (SG, RV), p. 749.
DATE-2000-OuaissV #configuration management #performance
Efficient Resource Arbitration in Reconfigurable Computing Environments (IO, RV), pp. 560–566.
DAC-1999-DoboliNDGV #behaviour #design #synthesis #using
Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration (AD, ANA, NRD, SG, RV), pp. 951–957.
DAC-1999-KaulVGO #approach #automation #clustering #configuration management #synthesis
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications (MK, RV, SG, IO), pp. 616–622.
DATE-1999-DhanwadaNV #constraints #synthesis #using
Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis (NRD, ANA, RV), p. 328–?.
DATE-1999-DoboliV #architecture #behaviour #compilation #generative #synthesis
A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems (AD, RV), pp. 338–345.
DATE-1999-KaulV #clustering #design #latency #runtime
Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs (MK, RV), pp. 202–209.
DATE-1999-MansouriV #design #verification
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs (NM, RV), p. 223–?.
DATE-1999-Nunez-AldanaV #effectiveness #performance #synthesis
An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis (ANA, RV), pp. 406–411.
DATE-1998-KaulV #architecture #clustering #configuration management #synthesis
Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures (MK, RV), pp. 389–396.
DATE-1998-SrinivasanRV #clustering #design #hardware
Hardware Software Partitioning with Integrated Hardware Design Space Exploration (VS, SR, RV), pp. 28–35.
DAC-1997-WalrathV #evaluation #modelling #performance #symbolic computation #trade-off #visualisation
Symbolic Evaluation of Performance Models for Tradeoff Visualization (JW, RV), pp. 359–364.
EDTC-1997-GovindarajanV #algorithm #clustering #heuristic
Cone-based clustering heuristic for list-scheduling algorithms (SG, RV), pp. 456–462.
EDTC-1997-WalrathVB #analysis #partial evaluation #performance #using #verification
Performance verification using partial evaluation and interval analysis (JW, RV, WB), p. 622.
DAC-1993-MandayamV #attribute grammar #performance #specification #using
Performance Specification Using Attributed Grammars (RM, RV), pp. 661–667.
DAC-1993-VemuriMSKRV #case study #experience #functional #synthesis #validation
Experiences in Functional Validation of a High Level Synthesis System (RV, PM, PS, NK, JR, RV), pp. 194–201.
DAC-1992-DuttaRV #distributed #synthesis
Distributed Design-Space Exploration for High-Level Synthesis Systems (RD, JR, RV), pp. 644–650.
CAV-1991-VemuriS #design #verification
Temporal Precondition Verification of Design Transformations (RV, AS), pp. 125–135.

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