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Collaborated with:
A.Demeure F.Jutand
Talks about:
parallel (1) address (1) system (1) scheme (1) memori (1)

Person: Céline Verdier

DBLP DBLP: Verdier:C=eacute=line

Contributed to:

PDP 19931993

Wrote 1 papers:

PDP-1993-VerdierDJ #memory management #parallel
Addressing scheme for a parallel memory system (CV, AD, FJ), pp. 131–135.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.