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Travelled to:
1 × USA
Collaborated with:
K.Yoshikawa H.Tanishita S.Suzuki N.Nomizu A.Kondoh
Talks about:
circuit (1) optim (1) time (1) map (1)

Person: Hiroshi Ichiryu

DBLP DBLP: Ichiryu:Hiroshi

Contributed to:

DAC 19911991

Wrote 1 papers:

DAC-1991-YoshikawaITSNK #optimisation
Timing Optimization on Mapped Circuits (KY, HI, HT, SS, NN, AK), pp. 112–117.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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