BibSLEIGH — circuit stem

Used together with:

design (169)
analog (149)
simul (131)
use (131)
base (129)

Stem circuit$ (all stems)

1299 papers:

DAC-2015-ChenH #equivalence #logic #probability: Equivalence among stochastic logic circuits and its application (THC, JPH), p. 6.
DAC-2015-CiesielskiYBLR #verification: Verification of gate-level arithmetic circuits by function extraction (MJC, CY, WB, DL, AR), p. 6.
DAC-2015-DaiKB #equivalence: Sequential equivalence checking of clock-gated circuits (YYD, KYK, RKB), p. 6.
DAC-2015-DunbarQ: A practical circuit fingerprinting method utilizing observability don’t care conditions (CD, GQ), p. 6.
DAC-2015-GuoTFD #anti #obfuscation #reverse engineering: Investigation of obfuscation-based anti-reverse engineering for printed circuit boards (ZG, MT, DF, JD), p. 6.
DAC-2015-HanF #analysis #approach #cpu #gpu #graph #scalability: Transient-simulation guided graph sparsification approach to scalable harmonic balance (HB) analysis of post-layout RF circuits leveraging heterogeneous CPU-GPU computing systems (LH, ZF), p. 6.
DAC-2015-HelalBH #parallel #simulation #using: Parallel circuit simulation using the direct method on a heterogeneous cloud (AEH, AMB, YYH), p. 6.
DAC-2015-HeyseS: Avoiding transitional effects in dynamic circuit specialisation on FPGAs (KH, DS), p. 6.
DAC-2015-HuangFYZL #estimation #multi #performance: Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits (QH, CF, FY, XZ, XL), p. 6.
DAC-2015-LahiouelZT #smt #towards #using: Towards enhancing analog circuits sizing using SMT-based techniques (OL, MHZ, ST), p. 6.
DAC-2015-LiuLLWLMLCJ0SY #energy: Ambient energy harvesting nonvolatile processors: from circuit to system (YL, ZL, HL, YW, XL, KM, SL, MFC, SJ, YX, JS, HY), p. 6.
DAC-2015-MiuraFNHHA #concept: EM attack sensor: concept, circuit, and design-automation methodology (NM, DF, MN, NH, YiH, TA), p. 6.
DAC-2015-TenaceCMP #logic #synthesis: One-pass logic synthesis for graphene-based Pass-XNOR logic circuits (VT, AC, EM, MP), p. 6.
DAC-2015-TodmanSL #configuration management #design #monitoring #runtime #verification: In-circuit temporal monitors for runtime verification of reconfigurable designs (TT, SS, WL), p. 6.
DAC-2015-ZaheerWGL #markov #named #performance #process: mTunes: efficient post-silicon tuning of mixed-signal/RF integrated circuits based on Markov decision process (MZ, FW, CG, XL), p. 6.
DAC-2015-ZhuangYKWC #algorithm #exponential #framework #performance #scalability #simulation #using: An algorithmic framework for efficient large-scale circuit simulation using exponential integrators (HZ, WY, IK, XW, CKC), p. 6.
DATE-2015-AfacanBPDB #hybrid #monte carlo: A hybrid Quasi Monte Carlo method for yield aware analog circuit sizing tool (EA, GB, AEP, GD, IFB), pp. 1225–1228.
DATE-2015-AhmadyanGNCV #analysis #diagrams #performance: Fast eye diagram analysis for high-speed CMOS circuits (SNA, CG, SN, EC, SV), pp. 1377–1382.
DATE-2015-CaoBFCCAO #feature model #validation: LVS check for photonic integrated circuits: curvilinear feature extraction and validation (RC, JB, JF, LC, JC, AA, IO), pp. 1253–1256.
DATE-2015-ChenWY #parallel #performance: A fast parallel sparse solver for SPICE-based circuit simulators (XC, YW, HY), pp. 205–210.
DATE-2015-CilingirogluZUK #representation: Dictionary-based sparse representation for resolution improvement in laser voltage imaging of CMOS integrated circuits (TBC, MZ, AU, WCK, JK, AJ, BBG, MSÜ), pp. 597–600.
DATE-2015-FuggerNNS #modelling #physics #towards: Towards binary circuit models that faithfully capture physical solvability (MF, RN, TN, US), pp. 1455–1460.
DATE-2015-GoncalvesLCTCB #algorithm #modelling #performance #reduction: A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits (HRG, XL, MVC, VT, JMCJ, KMB), pp. 1042–1047.
DATE-2015-JiaoMD #reasoning #synthesis: Knowledge-intensive, causal reasoning for analog circuit topology synthesis in emergent and innovative applications (FJ, SM, AD), pp. 1144–1149.
DATE-2015-KriebelRSASH #analysis #combinator #configuration management #fault #named #performance: ACSEM: accuracy-configurable fast soft error masking analysis in combinatorial circuits (FK, SR, DS, PVA, MS, JH), pp. 824–829.
DATE-2015-KumarLSSH #adaptation #verification: Timing verification for adaptive integrated circuits (RK, BL, YS, US, JH), pp. 1587–1590.
DATE-2015-LiXWNP #fine-grained #multi #power management #reduction #using: Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique (JL, QX, YW, SN, MP), pp. 1579–1582.
DATE-2015-MamaghaniGE #named: De-elastisation: from asynchronous dataflows to synchronous circuits (MJM, JDG, DAE), pp. 273–276.
DATE-2015-MazloumiM #hybrid #memory management #multi: A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors (AM, MM), pp. 908–911.
DATE-2015-MohammadiGM #fault #modelling: Fault modeling in controllable polarity silicon nanowire circuits (HGM, PEG, GDM), pp. 453–458.
DATE-2015-PajouhiFR #architecture #co-evolution #design #reliability: Device/circuit/architecture co-design of reliable STT-MRAM (ZP, XF, KR), pp. 1437–1442.
DATE-2015-SaifhashemiHBB #equivalence #logic #tool support #using: Logical equivalence checking of asynchronous circuits using commercial tools (AS, HHH, PB, PAB), pp. 1563–1566.
DATE-2015-SalfelderH #adaptation #evaluation #simulation #using: Ageing simulation of analogue circuits and systems using adaptive transient evaluation (FS, LH), pp. 1261–1264.
DATE-2015-SalivaCHFABBA #monitoring #reliability: Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI (MS, FC, VH, XF, DA, AB, AB, LA), pp. 441–446.
DATE-2015-SuHL #encoding #named #recognition #scalability: SubHunter: a high-performance and scalable sub-circuit recognition method with Prüfer-encoding (HYS, CHH, YLL), pp. 1583–1586.
DATE-2015-SunKPE #algebra #geometry #using #verification: Formal verification of sequential Galois field arithmetic circuits using algebraic geometry (XS, PK, TP, FE), pp. 1623–1628.
DATE-2015-WeiDLW #metaprogramming: A universal macro block mapping scheme for arithmetic circuits (XW, YD, TKL, YLW), pp. 1629–1634.
DATE-2015-WengCCHW #using: Using structural relations for checking combinationality of cyclic circuits (WCW, YCC, JHC, CYH, CYW), pp. 325–328.
DATE-2015-ZhaoQ #design #probability #synthesis: A general design of stochastic circuit and its synthesis (ZZ, WQ), pp. 1467–1472.
DRR-2015-DeMDC #detection #documentation #image: Detection of electrical circuit elements from documents images (PD, SM, AKD, BC).
PLDI-2015-LongfieldNMT #self #specification: Preventing glitches and short circuits in high-level self-timed chip specifications (SLJ, BN, RM, RT), pp. 270–279.
STOC-2015-BaconFHS #quantum: Sparse Quantum Codes from Quantum Circuits (DB, STF, AWH, JS), pp. 327–334.
ICALP-v1-2015-BunT #approximate: Hardness Amplification and the Approximate Degree of Constant-Depth Circuits (MB, JT), pp. 268–280.
ICALP-v1-2015-KomarathSS #bound #finite: Comparator Circuits over Finite Bounded Posets (BK, JS, KSS), pp. 834–845.
ICALP-v2-2015-AmarilliBS: Provenance Circuits for Trees and Treelike Instances (AA, PB, PS), pp. 56–68.
LATA-2015-AmanoS #bound #multi #polynomial: A Nonuniform Circuit Class with Multilayer of Threshold Gates Having Super Quasi Polynomial Size Lower Bounds Against NEXP (KA, AS), pp. 461–472.
SAC-2015-Kerschbaum #generative #outsourcing: Oblivious outsourcing of garbled circuit generation (FK), pp. 2134–2140.
DAC-2014-AkgulPLBPBT #power management: Power management through DVFS and dynamic body biasing in FD-SOI circuits (YA, DP, SL, EB, IMP, PB, LT), p. 6.
DAC-2014-AndraudSS: One-Shot Calibration of RF Circuits Based on Non-Intrusive Sensors (MA, HGDS, ES), p. 2.
DAC-2014-ChuangLJ #hybrid #synthesis: Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits (CCC, YHL, JHRJ), p. 6.
DAC-2014-CocchiBCW #hardware #integration: Circuit Camouflage Integration for Hardware IP Protection (RPC, JPB, LWC, BJW), p. 5.
DAC-2014-DengBZW #performance: An Efficient Two-level DC Operating Points Finder for Transistor Circuits (JD, KB, YZ, NW), p. 6.
DAC-2014-FangYZL #estimation #named #performance: BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits (CF, FY, XZ, XL), p. 6.
DAC-2014-KabirS #hybrid: Computing with Hybrid CMOS/STO Circuits (MK, MRS), p. 6.
DAC-2014-KiamehrOTN #analysis #approach #fault: Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit Approach (SK, THO, MBT, SRN), p. 6.
DAC-2014-LiS #monitoring #pipes and filters #robust #self: Robust and In-Situ Self-Testing Technique for Monitoring Device Aging Effects in Pipeline Circuits (JL, MS), p. 6.
DAC-2014-LiuCHWXY #3d #design: Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case (WL, GC, XH, YW, YX, HY), p. 6.
DAC-2014-MukherjeeAL #approximate: Approximate property checking of mixed-signal circuits (PM, CSA, PL), p. 6.
DAC-2014-MukherjeeL: Leveraging pre-silicon data to diagnose out-of-specification failures in mixed-signal circuits (PM, PL), p. 6.
DAC-2014-PrussKE #abstraction #equivalence #scalability #using #verification: Equivalence Verification of Large Galois Field Arithmetic Circuits using Word-Level Abstraction via Gröbner Bases (TP, PK, FE), p. 6.
DAC-2014-WaksmanRSS #analysis #assessment #functional #identification: A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification (AW, JR, MS, SS), p. 4.
DAC-2014-WuXKCH #named #simulation #statistics #towards: REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage (WW, WX, RK, YLC, LH), p. 6.
DATE-2014-AlaghiH #performance #probability #using: Fast and accurate computation using stochastic circuits (AA, JPH), pp. 1–4.
DATE-2014-BeckerNI #named #sketching: SKETCHILOG: Sketching combinational circuits (AB, DN, PI), pp. 1–4.
DATE-2014-BurlyaevFG: Verification-guided voter minimization in triple-modular redundant circuits (DB, PF, AG), pp. 1–6.
DATE-2014-ChangOSK #approximate #estimation #statistics: Approximating the age of RF/analog circuits through re-characterization and statistical estimation (DC, SO, OS, RK), pp. 1–4.
DATE-2014-ChenLLSHC #3d: Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits (YGC, KYL, MCL, YS, WKH, SCC), pp. 1–4.
DATE-2014-CortezRHN #testing: Testing PUF-based secure key storage circuits (MC, GR, SH, GDN), pp. 1–6.
DATE-2014-FerentD #comparison #mining #novel #synthesis #using: Novel circuit topology synthesis method using circuit feature mining and symbolic comparison (CF, AD), pp. 1–4.
DATE-2014-JinS #evaluation #realtime #trust: Real-time trust evaluation in integrated circuits (YJ, DS), pp. 1–6.
DATE-2014-LinWCH #logic: Rewiring for threshold logic circuit minimization (CCL, CYW, YCC, CYH), pp. 1–6.
DATE-2014-NejatAA #power management #process: Dynamic Flip-Flop conversion to tolerate process variation in low power circuits (MN, BA, AAK), pp. 1–4.
DATE-2014-NepalLBR #approximate #automation #behaviour #named #synthesis: ABACUS: A technique for automated behavioral synthesis of approximate computing circuits (KN, YL, RIB, SR), pp. 1–6.
DATE-2014-OrtinGVIV: Dynamic construction of circuits for reactive traffic in homogeneous CMPs (MO, DSG, MV, CI, VV), pp. 1–4.
DATE-2014-PalerDNP #fault tolerance #quantum: Software-based Pauli tracking in fault-tolerant quantum circuits (AP, SJD, KN, IP), pp. 1–4.
DATE-2014-PerriconeHNN #3d #case study #design #logic: Design of 3D nanomagnetic logic circuits: A full-adder case study (RP, XSH, JN, MTN), pp. 1–6.
DATE-2014-RanjanRVRR #approximate #named #synthesis: ASLAN: Synthesis of approximate sequential circuits (AR, AR, SV, KR, AR), pp. 1–6.
DATE-2014-ReimerSSB #using: Using MaxBMC for Pareto-optimal circuit initialization (SR, MS, TS, BB), pp. 1–6.
DATE-2014-RichterVSHV #challenge: Integrated circuits processing chemical information: Prospects and challenges (AR, AV, RS, SH, MV), p. 1.
DATE-2014-SongDY #analysis #bound #multi #order #parametricity #performance #reduction: Zonotope-based nonlinear model order reduction for fast performance bound analysis of analog circuits with multiple-interval-valued parameter variations (YS, SMPD, HY), pp. 1–6.
DATE-2014-SwaminathanKCSPSN #architecture #modelling: Modeling steep slope devices: From circuits to architectures (KS, MSK, NC, BS, RP, JS, VN), pp. 1–6.
DATE-2014-TenaceCMP #logic: Pass-XNOR logic: A new logic style for P-N junction based graphene circuits (VT, AC, EM, MP), pp. 1–4.
DATE-2014-Velasco-JimenezCRF #composition #implementation #modelling #performance: Implementation issues in the hierarchical composition of performance models of analog circuits (MVJ, RCL, ER, FVF), pp. 1–6.
DATE-2014-WeberTGHKM #challenge #configuration management: Reconfigurable silicon nanowire devices and circuits: Opportunities and challenges (WMW, JT, MG, AH, MK, TM), pp. 1–6.
DATE-2014-ZangenehJ #design #feedback #logic #using: Sub-threshold logic circuit design using feedback equalization (MZ, AJ), pp. 1–6.
ESOP-2014-YoshimizuHFL #higher-order #metric #proving #quantum: Measurements in Proof Nets as Higher-Order Quantum Circuits (AY, IH, CF, UDL), pp. 371–391.
STOC-2014-ArtemenkoS #generative #pseudo: Pseudorandom generators with optimal seed length for non-boolean poly-size circuits (SA, RS), pp. 99–108.
STOC-2014-GenkinIPST: Circuits resilient to additive attacks with applications to secure computation (DG, YI, MP, AS, ET), pp. 495–504.
STOC-2014-Rossman #distance: Formulas vs. circuits for small distance connectivity (BR), pp. 203–212.
STOC-2014-Sherstov: Breaking the minsky-papert barrier for constant-depth circuits (AAS), pp. 223–232.
STOC-2014-Williams #algorithm #bound #linear: New algorithms and lower bounds for circuits with linear threshold gates (RW), pp. 194–202.
STOC-2014-Williams14a #complexity #performance: Faster all-pairs shortest paths via circuit complexity (RW), pp. 664–673.
AFL-2014-Valdats #complexity #regular expression: Boolean Circuit Complexity of Regular Languages (MV), pp. 342–354.
ICALP-v1-2014-KumarS #bound: Superpolynomial Lower Bounds for General Homogeneous Depth 4 Arithmetic Circuits (MK, SS), pp. 751–762.
ICGT-2014-KreowskiKLL #evaluation #generative #graph transformation #synthesis: Graph Transformation Meets Reversible Circuits: Generation, Evaluation, and Synthesis (HJK, SK, AL, ML), pp. 237–252.
CHI-2014-HodgesVCCQNK #interactive #prototype: Circuit stickers: peel-and-stick construction of interactive electronic prototypes (SH, NV, NC, TC, JQ, DN, YK), pp. 1743–1746.
CHI-2014-QiB #design #sketching: Sketching in circuits: designing and building electronics on paper (JQ, LB), pp. 1713–1722.
DUXU-DI-2014-FrankjaerG #hybrid #network #smarttech: Wearable Networks, Creating Hybrid Spaces with Soft Circuits (TRF, DG), pp. 435–445.
CASE-2013-ChenTSPSSN #design #optimisation: Optimization processing unit (OPU) applied to integrated circuit design and manufacturing (DCLC, JTT, DBS, SWP, MHS, KTS, PN), pp. 1008–1015.
DAC-2013-AbousamraJM #multi: Proactive circuit allocation in multiplane NoCs (AA, AKJ, RGM), p. 10.
DAC-2013-AlaghiLH #probability #realtime: Stochastic circuits for real-time image-processing applications (AA, CL, JPH), p. 6.
DAC-2013-DoustiP #algorithm #estimation #latency #named #quantum: LEQA: latency estimation for a quantum algorithm mapped to a quantum circuit fabric (MJD, MP), p. 7.
DAC-2013-Fang #simulation: A new time-stepping method for circuit simulation (GPF), p. 10.
DAC-2013-HanZF #gpu #named #parallel #simulation: TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulations (LH, XZ, ZF), p. 8.
DAC-2013-HoOCT #array: Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits (KHH, HCO, YWC, HFT), p. 6.
DAC-2013-HsuCHCC #design: Routability-driven placement for hierarchical mixed-size circuit designs (MKH, YFC, CCH, TCC, YWC), p. 6.
DAC-2013-LinLM #analysis #hybrid #kernel #reachability #verification: Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis (HL, PL, CJM), p. 6.
DAC-2013-ShafaeiSP #architecture #distance #interactive #linear #nearest neighbour #optimisation #quantum: Optimization of quantum circuits for interaction distance in linear nearest neighbor architectures (AS, MS, MP), p. 6.
DAC-2013-WangZSLG #modelling #performance #reuse #scalability: Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data (FW, WZ, SS, XL, CG), p. 6.
DAC-2013-YeYSJX #generative: Post-placement voltage island generation for timing-speculative circuits (RY, FY, ZS, WBJ, QX), p. 6.
DAC-2013-YuanLJX #on the #testing: On testing timing-speculative circuits (FY, YL, WBJ, QX), p. 6.
DAC-2013-YuanX #fault #logic #low cost #named #scalability: InTimeFix: a low-cost and scalable technique for in-situ timing error masking in logic circuits (FY, QX), p. 6.
DAC-2013-ZhouLJ #3d #complexity #finite #linear #multi #scalability: A direct finite element solver of linear complexity for large-scale 3-D circuit extraction in multiple dielectrics (BZ, HL, DJ), p. 6.
DATE-2013-0001WAWG #3d #energy #modelling: System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs (KC, CW, BA, NW, KG), pp. 236–241.
DATE-2013-AhmadyanKV #algorithm #incremental #runtime #using #verification: Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm (SNA, JAK, SV), pp. 21–26.
DATE-2013-AhmadyanV #analysis #reachability #reduction #set: Reachability analysis of nonlinear analog circuits through iterative reachable set reduction (SNA, SV), pp. 1436–1441.
DATE-2013-AmaruGM #canonical #logic #novel #synthesis: Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits (LGA, PEG, GDM), pp. 1014–1017.
DATE-2013-BernasconiCTV #using: Minimization of P-circuits using Boolean relations (AB, VC, GT, TV), pp. 996–1001.
DATE-2013-ChenRSIFC #analysis #process: A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation (YYC, AR, AS, GI, GF, DC), pp. 1789–1794.
DATE-2013-ChenWLL #automation #flexibility #process: Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects (YLC, WRW, GRL, CNJL), pp. 1458–1461.
DATE-2013-FarisiBCS #automation #implementation #multi: An automatic tool flow for the combined implementation of multi-mode circuits (BAF, KB, JMPC, DS), pp. 821–826.
DATE-2013-GielenM #modelling #probability #simulation: Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS (GGEG, EM), pp. 326–331.
DATE-2013-HellwegeHPP #analysis #metric #reliability: Reliability analysis for integrated circuit amplifiers used in neural measurement systems (NH, NH, DPD, SP), pp. 713–716.
DATE-2013-JongheDDG #modelling #recursion: Extracting analytical nonlinear models from analog circuits by recursive vector fitting of transfer function trajectories (DdJ, DD, TD, GGEG), pp. 1448–1453.
DATE-2013-JoshiLBBG #estimation #performance #statistics: A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits (SJ, AL, MB, EB, SG), pp. 1056–1057.
DATE-2013-MillerB #parametricity #satisfiability #verification: Formal verification of analog circuit parameters across variation utilizing SAT (MM, FB), pp. 1442–1447.
DATE-2013-MishraBTRF #energy #power management: A sub-μa power management circuit in 0.18μm CMOS for energy harvesters (BM, CB, GT, CR, PAF), pp. 1197–1202.
DATE-2013-PalitHNN #design #logic: Systematic design of nanomagnet logic circuits (IP, XSH, JN, MTN), pp. 1795–1800.
DATE-2013-PanCL #agile #design #named #parallel #performance #search-based #towards: PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design (PCP, HMC, CCL), pp. 1849–1854.
DATE-2013-RenPRKWEK #performance #synthesis: Intuitive ECO synthesis for high performance circuits (HR, RP, LNR, SK, CW, JE, JK), pp. 1002–1007.
DATE-2013-SubramanyanTPRSM #analysis #functional #reverse engineering #using: Reverse engineering digital circuits using functional analysis (PS, NT, KP, DR, AS, SM), pp. 1277–1280.
DATE-2013-SureshYOS #adaptation #multi #reduction: Adaptive reduction of the frequency search space for multi-vdd digital circuits (CKHS, EY, SO, OS), pp. 292–295.
DATE-2013-VenkataramaniRR #approximate #configuration management #design #named #paradigm #quality: Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits (SV, KR, AR), pp. 1367–1372.
DATE-2013-WeiSHCLLZWM #challenge: Carbon nanotube circuits: opportunities and challenges (HW, MMS, GH, HYC, CSL, LL, JZ, HSPW, SM), pp. 619–624.
DATE-2013-YilmazSWO #analysis #fault #industrial #scalability #simulation: Fault analysis and simulation of large scale industrial mixed-signal circuits (EY, GS, LW, SO), pp. 565–570.
STOC-2013-GoldwasserKPVZ #encryption #functional #reuse: Reusable garbled circuits and succinct functional encryption (SG, YTK, RAP, VV, NZ), pp. 555–564.
STOC-2013-GorbunovVW #encryption: Attribute-based encryption for circuits (SG, VV, HW), pp. 545–554.
STOC-2013-MilesV: Shielding circuits with groups (EM, EV), pp. 251–260.
ICALP-v1-2013-KumarMN #bound: Arithmetic Circuit Lower Bounds via MaxRank (MK, GM, JS), pp. 661–672.
PPDP-2013-ODonnell #array #functional #parallel: Extensible sparse functional arrays with circuit parallelism (JTO), pp. 133–144.
CASE-2012-HanXZLW #concurrent #policy: Two-stage deadlock prevention policy based on resource-transition circuits (LH, KX, MZ, HL, FW), pp. 741–746.
CASE-2012-WuHYC #component #integration: Pressure-drop studies of resistance components for integration into a SFM-based fluidic circuit (CHW, YFH, ASY, PHC), pp. 896–899.
DAC-2012-AadithyaR #abstraction #automation #automaton #generative #logic #named: DAE2FSM: automatic generation of accurate discrete-time logical abstractions for continuous-time circuit dynamics (KVA, JSR), pp. 311–316.
DAC-2012-AhmadyanKV #generative: Goal-oriented stimulus generation for analog circuits (SNA, JAK, SV), pp. 1018–1023.
DAC-2012-ChouHC #design: Structure-aware placement for datapath-intensive circuit designs (SC, MKH, YWC), pp. 762–767.
DAC-2012-JungCK #optimisation #variability: Variability-aware, discrete optimization for analog circuits (SJ, YC, JK), pp. 536–541.
DAC-2012-KuoHCKC #design #monte carlo #performance: Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits (CCK, WYH, YHC, JFK, YKC), pp. 1113–1118.
DAC-2012-LeeKYBS #design #guidelines #power management: Circuit and system design guidelines for ultra-low power sensor nodes (YL, YK, DY, DB, DS), pp. 1037–1042.
DAC-2012-MorrisBZP #logic #named #using: mLogic: ultra-low voltage non-volatile logic circuits using STT-MTJ devices (DM, DB, JG(Z, LTP), pp. 486–491.
DAC-2012-ParkGMRR #architecture #design #energy #performance #using: Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture (SPP, SKG, NNM, AR, KR), pp. 492–497.
DAC-2012-RenCWZY #gpu #parallel #simulation: Sparse LU factorization for parallel circuit simulation on GPU (LR, XC, YW, CZ, HY), pp. 1125–1130.
DAC-2012-SasanianWM #quantum #using: Realizing reversible circuits using a new class of quantum gates (ZS, RW, DMM), pp. 36–41.
DAC-2012-Seok #design: Decoupling capacitor design strategy for minimizing supply noise of ultra low voltage circuits (MS), pp. 968–973.
DAC-2012-SuYZ #named #order #performance #reduction: AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuits (YS, FY, XZ), pp. 295–300.
DAC-2012-VenkataramaniSKRR #approximate #logic #named #synthesis: SALSA: systematic logic synthesis of approximate circuits (SV, AS, VJK, KR, AR), pp. 796–801.
DAC-2012-YeC #3d #fault: TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation (FY, KC), pp. 1024–1030.
DAC-2012-ZhaoF #on the fly #performance #simulation #towards: Towards efficient SPICE-accurate nonlinear circuit simulation with on-the-fly support-circuit preconditioners (XZ, ZF), pp. 1119–1124.
DATE-2012-AbdallahSMA #testing: Testing RF circuits with true non-intrusive built-in sensors (LA, HGDS, SM, JA), pp. 1090–1095.
DATE-2012-AridhiZT #order #reduction #simulation #towards #using: Towards improving simulation of analog circuits using model order reduction (HA, MHZ, ST), pp. 1337–1342.
DATE-2012-DoustiP #latency #quantum: Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric (MJD, MP), pp. 840–843.
DATE-2012-HeuserSS #modelling: Revealing side-channel issues of complex circuits by enhanced leakage models (AH, WS, MS), pp. 1179–1184.
DATE-2012-KarimiCGP #fault #generative #testing: Test generation for clock-domain crossing faults in integrated circuits (NK, KC, PG, SP), pp. 406–411.
DATE-2012-LiH #analysis #logic #named #performance #reliability: RAG: An efficient reliability analysis of logic circuits on graphics processing units (ML, MSH), pp. 316–319.
DATE-2012-LiuJL #constant #parallel: Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC (SL, AJ, ZL), pp. 1289–1294.
DATE-2012-LiuMG #estimation #performance #problem: A fast analog circuit yield estimation method for medium and high dimensional problems (BL, JM, GGEG), pp. 751–756.
DATE-2012-LiuTW #analysis #approach #graph #parallel #statistics: Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach (XL, SXDT, HW), pp. 852–857.
DATE-2012-MaricauJG #analysis #learning #multi #reliability #using: Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection (EM, DdJ, GGEG), pp. 745–750.
DATE-2012-MeissnerMLH #framework #graph #morphism #performance #synthesis #testing: Fast isomorphism testing for a graph-based analog circuit synthesis framework (MM, OM, LL, LH), pp. 757–762.
DATE-2012-PanagopoulosAR #approach #framework #hybrid #simulation: A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach (GP, CA, KR), pp. 1443–1446.
DATE-2012-SekaninaV #optimisation #polymorphism #satisfiability: A SAT-based fitness function for evolutionary optimization of polymorphic circuits (LS, ZV), pp. 715–720.
DATE-2012-WangLPW #algorithm #difference #linear #simulation: An operational matrix-based algorithm for simulating linear and fractional differential circuits (YW, HL, GKHP, NW), pp. 1463–1466.
DATE-2012-WilleDOO #automation #design #power management #synthesis #using: Automatic design of low-power encoders using reversible circuit synthesis (RW, RD, CO, AGO), pp. 1036–1041.
DATE-2012-YangLTW #modelling: Almost every wire is removable: A modeling and solution for removing any circuit wire (XY, TKL, WCT, YLW), pp. 1573–1578.
DATE-2012-YordanovAGGCBHBD #biology #verification: Experimentally driven verification of synthetic biological circuits (BY, EA, RG, EAG, SBC, SB, TH, CB, DD), pp. 236–241.
STOC-2012-AgrawalSSS #bound: Jacobian hits circuits: hitting-sets, lower bounds for depth-D occur-k formulas & depth-3 transcendence degree-k circuits (MA, CS, RS, NS), pp. 599–614.
STOC-2012-GalHKPV #bound: Tight bounds on computing error-correcting codes by bounded-depth circuits with arbitrary gates (AG, KAH, MK, PP, EV), pp. 479–494.
STOC-2012-GuptaKL #multi #re-engineering: Reconstruction of depth-4 multilinear circuits with top fan-in 2 (AG, NK, SVL), pp. 625–642.
LATA-2012-ArvindV #morphism #testing: Isomorphism Testing of Boolean Functions Computable by Constant-Depth Circuits (VA, YV), pp. 83–94.
LATA-2012-Noual: Dynamics of Circuits and Intersecting Circuits (MN), pp. 433–444.
ICML-2012-HannahD #design #geometry #programming: Ensemble Methods for Convex Regression with Applications to Geometric Programming Based Circuit Design (LH, DBD), p. 24.
CAV-2012-GuetGHMS #markov #search-based: Delayed Continuous-Time Markov Chains for Genetic Regulatory Circuits (CCG, AG, TAH, MM, AS), pp. 294–309.
CAV-2012-Myers #search-based #verification: Formal Verification of Genetic Circuits (CJM), p. 5.
ICLP-2012-FilardoE #finite #flexibility: A Flexible Solver for Finite Arithmetic Circuits (NWF, JE), pp. 425–438.
SAT-2012-JarvisaloKKK #performance: Finding Efficient Circuits for Ensemble Computation (MJ, PK, MK, JHK), pp. 369–382.
DAC-2011-DensmoreHKSAWV #biology #design #synthesis: Joint DAC/IWBDA special session design and synthesis of biological circuits (DD, MH, SK, XS, AA, EW, CV), pp. 114–115.
DAC-2011-GongYH #analysis #monte carlo #orthogonal #performance #probability: Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials (FG, HY, LH), pp. 298–303.
DAC-2011-HaoTSS #analysis #bound #performance #process: Performance bound analysis of analog circuits considering process variations (ZH, SXDT, RS, GS), pp. 310–315.
DAC-2011-LinLCHC #random: Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits (CWL, JML, YCC, CPH, SJC), pp. 528–533.
DAC-2011-LiuYX #low cost: Re-synthesis for cost-efficient circuit-level timing speculation (YL, FY, QX), pp. 158–163.
DAC-2011-MukherjeeFBL #automation #linear #scalability: Automatic stability checking for large linear analog integrated circuits (PM, GPF, RB, PL), pp. 304–309.
DAC-2011-VelamalaLTC #design #logic: Design sensitivity of single event transients in scaled logic circuits (JV, RL, MT, YC), pp. 694–699.
DAC-2011-Warnock #challenge #design: Circuit design challenges at the 14nm technology node (JDW), pp. 464–467.
DAC-2011-WeiP #security #using: Integrated circuit security techniques using variable supply voltage (SW, MP), pp. 248–253.
DATE-2011-AvinashENPP #design #energy #probability: Energy parsimonious circuit design through probabilistic pruning (LA, CCE, JLN, KVP, CP), pp. 764–769.
DATE-2011-BalasubramanianSMNDKMPPVT #low cost #power management #robust: Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system (LB, PS, RKM, PN, RKD, ADK, SM, SP, HP, RCV, ST), pp. 551–554.
DATE-2011-BoosNSHHGKS #analysis: Strategies for initial sizing and operating point analysis of analog circuits (VB, JN, MS, SH, SH, HG, DK, RS), pp. 1672–1674.
DATE-2011-ChenZD #optimisation: Integrated circuit white space redistribution for temperature optimization (YC, HZ, RPD), pp. 613–618.
DATE-2011-FazeliAMAT #estimation #fault #multi: Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs) (MF, SNA, SGM, HA, MBT), pp. 70–75.
DATE-2011-FerentD #automation #design #similarity: A symbolic technique for automated characterization of the uniqueness and similarity of analog circuit design features (CF, AD), pp. 1212–1217.
DATE-2011-GielenMW #analysis #reliability: Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation (GGEG, EM, PHNDW), pp. 1474–1479.
DATE-2011-GraupnerJW #approach #design #generative #layout #optimisation: Generator based approach for analog circuit and layout design and optimization (AG, RJ, RW), pp. 1675–1680.
DATE-2011-HuangDEB #collaboration #communication #framework: A circuit technology platform for medical data acquisition and communication: Outline of a collaboration project within the Swiss Nano-Tera.ch Initiative (QH, CD, CE, TB), pp. 1472–1473.
DATE-2011-LiMY #independence: Redressing timing issues for speed-independent circuits in deep submicron age (YL, TSTM, AY), pp. 1376–1381.
DATE-2011-LiuHRG #optimisation #process #using: Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate model (BL, YH, PR, GGEG), pp. 1101–1106.
DATE-2011-MaricauG #analysis #probability #reliability: Stochastic circuit reliability analysis (EM, GGEG), pp. 1285–1290.
DATE-2011-MerrettAWZRMRLFA #analysis #modelling #monte carlo #performance #statistics #variability: Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis (MM, PA, YW, MZ, DR, CM, SR, ZL, SBF, AA), pp. 1537–1540.
DATE-2011-MiteaMHJ #automation #constraints #synthesis: Automated constraint-driven topology synthesis for analog circuits (OM, MM, LH, PJ), pp. 1662–1665.
DATE-2011-NarayananZT #correctness #pattern matching #process #using: Ensuring correctness of analog circuits in presence of noise and process variations using pattern matching (RN, MHZ, ST), pp. 1188–1191.
DATE-2011-NigamTZBM #nondeterminism #pseudo #representation: Pseudo circuit model for representing uncertainty in waveforms (AN, QT, AZ, MB, NvdM), pp. 1521–1524.
DATE-2011-ShinG #fault: A new circuit simplification method for error tolerant applications (DS, SKG), pp. 1566–1571.
DATE-2011-VasicekS #optimisation: A global postsynthesis optimization method for combinational circuits (ZV, LS), pp. 1525–1528.
DATE-2011-WilleKD #scalability: Determining the minimal number of lines for large reversible circuits (RW, OK, RD), pp. 1204–1207.
DATE-2011-YuH #fault #logic: Trigonometric method to handle realistic error probabilities in logic circuits (CCY, JPH), pp. 64–69.
ITiCSE-2011-SchaferMB #design #education: Design of innovative integrated circuits in education (AS, MM, RB), pp. 53–56.
STOC-2011-SarafV #black box #multi #testing: Black-box identity testing of depth-4 multilinear circuits (SS, IV), pp. 421–430.
STOC-2011-SaxenaS #bound #matter #testing: Blackbox identity testing for bounded top fanin depth-3 circuits: the field doesn’t matter (NS, CS), pp. 431–440.
CIAA-J-2010-Birget11 #on the: On the Circuit-Size of inverses (JCB), pp. 1925–1938.
ICALP-v1-2011-FaustPV #how: Tamper-Proof Circuits: How to Trade Leakage for Tamper-Resilience (SF, KP, DV), pp. 391–402.
ICALP-v1-2011-HarkinsH #algorithm #bound #game studies #learning: Exact Learning Algorithms, Betting Games, and Circuit Lower Bounds (RCH, JMH), pp. 416–423.
ICALP-v1-2011-JansenS #constant #polynomial: Permanent Does Not Have Succinct Polynomial Size Arithmetic Circuits of Constant Depth (MJJ, RS), pp. 724–735.
ICALP-v1-2011-Mengel #constraints #problem: Characterizing Arithmetic Circuit Classes by Constraint Satisfaction Problems — (Extended Abstract) (SM), pp. 700–711.
GPCE-2011-Launchbury: Theorem-based circuit derivation in cryptol (JL), pp. 185–186.
ASPLOS-2011-HoangFJ #compilation: Exploring circuit timing-aware language and compilation (GH, RBF, RJ), pp. 345–356.
SAT-2011-BelovS #satisfiability: Minimally Unsatisfiable Boolean Circuits (AB, JPMS), pp. 145–158.
SAT-2011-BuningZB #normalisation #quantifier: Transformations into Normal Forms for Quantified Circuits (HKB, XZ, UB), pp. 245–258.
VMCAI-2011-Dill: Are Cells Asynchronous Circuits? — (Invited Talk) (DLD), p. 1.
DAC-2010-BeeceXVZL #parametricity: Transistor sizing of custom high-performance digital circuits with parametric yield considerations (DKB, JX, CV, VZ, YL), pp. 781–786.
DAC-2010-GolubitskyFM #synthesis: Synthesis of the optimal 4-bit reversible circuits (OG, SMF, DM), pp. 653–656.
DAC-2010-HsuLML #analysis #flexibility: Static timing analysis for flexible TFT circuits (CHH, CL, EHM, JCML), pp. 799–802.
DAC-2010-KuoCTCL #approach #behaviour: Behavior-level yield enhancement approach for large-scaled analog circuits (CCK, YLC, ICT, LYC, CNJL), pp. 903–908.
DAC-2010-SeomunSS #implementation #power management #synthesis: Synthesis and implementation of active mode power gating circuits (JS, IS, YS), pp. 487–492.
DAC-2010-TruongB #architecture #design #manycore #modelling: Circuit modeling for practical many-core architecture design exploration (DT, BMB), pp. 627–628.
DAC-2010-WilleSD: Reducing the number of lines in reversible circuits (RW, MS, RD), pp. 647–652.
DAC-2010-YeL #modelling #optimisation #parallel #performance #runtime #simulation: Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation (XY, PL), pp. 561–566.
DAC-2010-ZhangBPLWMM #correlation: Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement (JZ, SB, NP, AL, HSPW, GDM, SM), pp. 889–892.
DAC-2010-ZhangCTL #modelling #multi #performance #scalability #towards: Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression (WZ, THC, MYT, XL), pp. 897–902.
DATE-2010-AziziMSPH #architecture #design #framework: An integrated framework for joint design space exploration of microarchitecture and circuits (OA, AM, JPS, SJP, MH), pp. 250–255.
DATE-2010-DadgourB #architecture #design #detection #novel #pipes and filters #using: Aging-resilient design of pipelined architectures using novel detection and correction circuits (HFD, KB), pp. 244–249.
DATE-2010-GanapathyCGR #estimation #modelling #multi #variability: Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability (SG, RC, AG, AR), pp. 417–422.
DATE-2010-GomezSBF: Analog circuit test based on a digital signature (AG, RS, LB, JF), pp. 1641–1644.
DATE-2010-HenryN #power management: From transistors to MEMS: Throughput-aware power gating in CMOS circuits (MBH, LN), pp. 130–135.
DATE-2010-HuangSM #fault #machine learning: Fault diagnosis of analog circuits based on machine learning (KH, HGDS, SM), pp. 1761–1766.
DATE-2010-JaffariA #estimation #monte carlo: Practical Monte-Carlo based timing yield estimation of digital circuits (JJ, MA), pp. 807–812.
DATE-2010-JaffariA10a #analysis #correlation #performance #variability: Correlation controlled sampling for efficient variability analysis of analog circuits (JJ, MA), pp. 1305–1308.
DATE-2010-JamaaMM #logic #power management: Power consumption of logic circuits in ambipolar carbon nanotube technology (MHBJ, KM, GDM), pp. 303–306.
DATE-2010-JeeraditKH #optimisation: Intent-leveraged optimization of analog circuits via homotopy (MJ, JK, MH), pp. 1614–1619.
DATE-2010-KrishnanDBK: Block-level bayesian diagnosis of analogue electronic circuits (SK, KDD, RB, HGK), pp. 1767–1772.
DATE-2010-LazzariFMC #multi: A new quaternary FPGA based on a voltage-mode multi-valued circuit (CL, PFF, JM, LC), pp. 1797–1802.
DATE-2010-LeeYCC #embedded #metric: An embedded wide-range and high-resolution CLOCK jitter measurement circuit (YL, CYY, NCDC, JJC), pp. 1637–1640.
DATE-2010-LiuFG #optimisation #performance: An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique (BL, FVF, GGEG), pp. 1106–1111.
DATE-2010-LongM10a #dependence #scheduling: Inversed Temperature Dependence aware clock skew scheduling for sequential circuits (JL, SOM), pp. 1657–1660.
DATE-2010-LotzeGM #modelling: Timing modeling for digital sub-threshold circuits (NL, JG, YM), pp. 299–302.
DATE-2010-MehdipourHKIKMAF #quantum #scalability: Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits (FM, HH, HK, KI, IK, KM, HA, AF), pp. 993–996.
DATE-2010-MintarnoSZVCBDM #self: Optimized self-tuning for circuit aging (EM, JS, RZ, JV, YC, SPB, RWD, SM), pp. 586–591.
DATE-2010-MishraJ #optimisation #power management #synthesis #using: Low-power FinFET circuit synthesis using surface orientation optimization (PM, NKJ), pp. 311–314.
DATE-2010-Mueller-GritschnederG #specification: Computation of yield-optimized Pareto fronts for analog integrated circuit specifications (DMG, HG), pp. 1088–1093.
DATE-2010-NarayananAZTP #process #verification: Formal verification of analog circuits in the presence of noise and process variation (RN, BA, MHZ, ST, LCP), pp. 1309–1312.
DATE-2010-PanYZS #approach #megamodelling #order #performance #reduction: An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits (XP, FY, XZ, YS), pp. 1673–1676.
DATE-2010-TajalliL #design #framework #power management #using: Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits (AT, YL), pp. 711–716.
DATE-2010-WatanabeA #modelling #multi #performance #simulation: Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation (TW, HA), pp. 1153–1158.
DATE-2010-WeerasekeraGPT #3d #on the: On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits (RW, MG, DP, HT), pp. 1325–1328.
DATE-2010-WuM #scheduling: Clock skew scheduling for soft-error-tolerant sequential circuits (KCW, DM), pp. 717–722.
DATE-2010-ZhangPLWM: Carbon nanotube circuits: Living with imperfections and variations (JZ, NP, AL, HSPW, SM), pp. 1159–1164.
ITiCSE-2010-ShoufanLR #framework #synthesis #visualisation: A platform for visualizing digital circuit synthesis with VHDL (AS, ZL, GR), pp. 294–298.
WRLA-2010-KatelmanKM #analysis #concurrent #semantics: Concurrent Rewriting Semantics and Analysis of Asynchronous Digital Circuits (MK, SK, JM), pp. 140–156.
STOC-2010-HrubesWY #commutative #problem: Non-commutative circuits and the sum-of-squares problem (PH, AW, AY), pp. 667–676.
STOC-2010-KarninMSV #bound #multi #testing: Deterministic identity testing of depth-4 multilinear circuits with bounded top fan-in (ZSK, PM, AS, IV), pp. 649–658.
STOC-2010-PaturiP #complexity #on the #satisfiability: On the complexity of circuit satisfiability (RP, PP), pp. 241–250.
LICS-2010-Milius #calculus #finite: A Sound and Complete Calculus for Finite Stream Circuits (SM), pp. 421–430.
SAT-2010-BelovS #satisfiability: Improved Local Search for Circuit Satisfiability (AB, ZS), pp. 293–299.
SAT-2010-GoultiaevaB: Exploiting Circuit Representations in QBF Solving (AG, FB), pp. 333–339.
TAP-2010-GoldbergM #encoding #generative #proving #testing: Generating High-Quality Tests for Boolean Circuits by Treating Tests as Proof Encoding (EG, PM), pp. 101–116.
DAC-2009-BawiecN #logic #synthesis: Boolean logic function synthesis for generalised threshold gate circuits (MAB, MN), pp. 83–86.
DAC-2009-BowmanTWLKDB: Circuit techniques for dynamic variation tolerance (KAB, JT, CW, SLL, TK, VD, SYB), pp. 4–7.
DAC-2009-BurnhamYH #probability: A stochastic jitter model for analyzing digital timing-recovery circuits (JRB, CKKY, HAH), pp. 116–121.
DAC-2009-ChoudhuryM #logic #lookahead #optimisation #using: Timing-driven optimization using lookahead logic circuits (MRC, KM), pp. 390–395.
DAC-2009-DasBBFA #design: Addressing design margins through error-tolerant circuits (SD, DB, DMB, KF, RA), pp. 11–12.
DAC-2009-DongL #integration #performance #simulation: Parallelizable stable explicit numerical integration for efficient circuit simulation (WD, PL), pp. 382–385.
DAC-2009-LiS #algorithm #optimisation #robust: Yield-driven iterative robust circuit optimization algorithm (YL, VS), pp. 599–604.
DAC-2009-LiuH #optimisation #parallel #performance: GPU-based parallelization for fast circuit optimization (YL, JH), pp. 943–946.
DAC-2009-ReddiGSWBC #challenge #hardware #reliability #stack: Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack (VJR, SC, MSG, MDS, GYW, DMB), pp. 788–793.
DAC-2009-RoyKG #interactive: Device/circuit interactions at 22nm technology node (KR, JPK, SKG), pp. 97–102.
DAC-2009-ShengXM #algorithm #fault #multi #optimisation #search-based #standard: Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm (WS, LX, ZM), pp. 502–507.
DAC-2009-SunNWS #composition #contract: Contract-based system-level composition of analog circuits (XS, PN, CCW, ALSV), pp. 605–610.
DAC-2009-TamPB #automation #validation: Automated failure population creation for validating integrated circuit diagnosis methods (WCT, OP, RD(B), pp. 708–713.
DAC-2009-YilmazO #adaptation: Adaptive test elimination for analog/RF circuits (EY, SO), pp. 720–725.
DAC-2009-ZhangCTL #performance #worst-case: Efficient design-specific worst-case corner extraction for integrated circuits (HZ, THC, MYT, XL), pp. 386–389.
DAC-2009-ZhangPHM: Carbon nanotube circuits in the presence of carbon nanotube density variations (JZ, NP, AH, SM), pp. 71–76.
DATE-2009-AliKWW #modelling #optimisation #performance: Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits (SA, LK, RW, PRW), pp. 712–717.
DATE-2009-BarkeGGHHPSW #formal method #verification: Formal approaches to analog circuit verification (EB, DG, HG, LH, SH, RP, SS, YW), pp. 724–729.
DATE-2009-ChiangOY: Register placement for high-performance circuits (MFC, TO, TY), pp. 1470–1475.
DATE-2009-ChoudhuryM #fault #logic: Masking timing errors on speed-paths in logic circuits (MRC, KM), pp. 87–92.
DATE-2009-DasV #approach #automation #design #grammarware #graph grammar #multi: A graph grammar based approach to automated multi-objective analog circuit design (AD, RV), pp. 700–705.
DATE-2009-DongCC #configuration management #design: Reconfigurable circuit design with nanomaterials (CD, SC, DC), pp. 442–447.
DATE-2009-GoyalSC #novel #self: A novel self-healing methodology for RF Amplifier circuits based on oscillation principles (AG, MS, AC), pp. 1656–1661.
DATE-2009-HolcombLS #analysis #design #fault: Design as you see FIT: System-level soft error analysis of sequential circuits (DEH, WL, SAS), pp. 785–790.
DATE-2009-MatsunagaHIMEOH #in memory: MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues (SM, JH, SI, KM, TE, HO, TH), pp. 433–435.
DATE-2009-MishraAZ #adaptation: Variation resilient adaptive controller for subthreshold circuits (BM, BMAH, MZ), pp. 142–147.
DATE-2009-MitraZPW #logic #using: Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors (SM, JZ, NP, HW), pp. 436–441.
DATE-2009-ModarressiSA #hybrid #network: A hybrid packet-circuit switched on-chip network based on SDM (MM, HSA, MA), pp. 566–569.
DATE-2009-PaikSS #named #performance #synthesis: HLS-l: High-level synthesis of high performance latch-based circuits (SP, IS, YS), pp. 1112–1117.
DATE-2009-PalmersMSG #multi: Massively multi-topology sizing of analog integrated circuits (PP, TM, MS, GGEG), pp. 706–711.
DATE-2009-PengC #parallel #simulation: Parallel transistor level full-chip circuit simulation (HP, CKC), pp. 304–307.
DATE-2009-SafizadehTATB #nondeterminism #using: Using randomization to cope with circuit uncertainty (HS, MT, EKA, GT, KB), pp. 815–820.
DATE-2009-WangM #using: An accurate interconnect thermal model using equivalent transmission line circuit (BW, PM), pp. 280–283.
DATE-2009-WilsonW #configuration management #variability: Optimal sizing of configurable devices to reduce variability in integrated circuits (PRW, RW), pp. 1385–1390.
ICALP-v1-2009-Amano #approximate #bound: Bounds on the Size of Small Depth Circuits for Approximating Majority (KA), pp. 59–70.
HIMI-II-2009-Matsak #logic #representation: Representing Logical Inference Steps with Digital Circuits (EM), pp. 178–184.
HPCA-2009-YehiaGBT #flexibility: Reconciling specialization and flexibility through compound circuits (SY, SG, HB, OT), pp. 277–288.
SAT-2009-BuningZB #quantifier #subclass: Resolution and Expressiveness of Subclasses of Quantified Boolean Formulas and Circuits (HKB, XZ, UB), pp. 391–397.
SAT-2009-GoultiaevaIB: Beyond CNF: A Circuit-Based QBF Solver (AG, VI, FB), pp. 412–426.
SAT-2009-KojevnikovKY #performance #using: Finding Efficient Circuits Using SAT-Solvers (AK, ASK, GY), pp. 32–44.
CASE-2008-FerrariniBV #approach #automation #case study #fault: A pragmatic approach to fault diagnosis in hydraulic circuits for automated machining: A case study (LF, RB, CV), pp. 29–34.
DAC-2008-CzajkowskiB #composition #linear #logic #synthesis: Functionally linear decomposition and synthesis of logic circuits for FPGAs (TSC, SDB), pp. 18–23.
DAC-2008-DasV #adaptation #synthesis: Topology synthesis of analog circuits based on adaptively generated building blocks (AD, RV), pp. 44–49.
DAC-2008-DongLY #manycore #named #parallel #simulation: WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines (WD, PL, XY), pp. 238–243.
DAC-2008-DongWSXLC #3d #architecture #evaluation #memory management #ram: Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement (XD, XW, GS, YX, HHL, YC), pp. 554–559.
DAC-2008-FranzonDSLOTMLDBSO #3d #design: Design and CAD for 3D integrated circuits (PDF, WRD, MBS, SL, ECO, TT, SM, SL, TD, SB, BS, KO), pp. 668–673.
DAC-2008-GuptaK #bound: Bounded-lifetime integrated circuits (PG, ABK), pp. 347–348.
DAC-2008-JamaaALM #logic #programmable: Programmable logic circuits based on ambipolar CNFET (MHBJ, DA, YL, GDM), pp. 339–340.
DAC-2008-JiangS #algorithm #scalability: Circuit-wise buffer insertion and gate sizing algorithm with scalability (ZJ, WS), pp. 708–713.
DAC-2008-KrishnaswamyMH #design #logic #on the #reliability: On the role of timing masking in reliable logic circuit design (SK, ILM, JPH), pp. 924–929.
DAC-2008-PaikS #multi #optimisation #standard: Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements (SP, YS), pp. 600–605.
DAC-2008-PangR #fixpoint #optimisation: Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform (YP, KR), pp. 397–402.
DAC-2008-ReddyPL #detection #on the #testing: On tests to detect via opens in digital CMOS circuits (SMR, IP, CL), pp. 840–845.
DATE-2008-AliWWB #approach #behaviour #modelling #performance: A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits (SA, RW, PRW, ADB), pp. 152–157.
DATE-2008-BadelGIMVGL #design #difference #standard: A Generic Standard Cell Design Methodology for Differential Circuit Styles (SB, EG, OI, APM, PV, FKG, YL), pp. 843–848.
DATE-2008-ChoudhuryM #approximate #concurrent #detection #fault #logic: Approximate logic circuits for low overhead, non-intrusive concurrent error detection (MRC, KM), pp. 903–908.
DATE-2008-EngelkePSB #fault #industrial #simulation: Resistive Bridging Fault Simulation of Industrial Circuits (PE, IP, JS, BB), pp. 628–633.
DATE-2008-FeinsteinTM #detection #equivalence #logic #using: Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits (DYF, MAT, DMM), pp. 1378–1381.
DATE-2008-GuiducciSGL #architecture #interface #novel: Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces (CG, AS, FKG, YL), pp. 1328–1333.
DATE-2008-KazmierskiZA #approximate #mobile #modelling #performance #using: Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density (TJK, DZ, BMAH), pp. 146–151.
DATE-2008-LeppeltB #complexity: Determining the Technical Complexity of Integrated Circuits (PL, EB), p. 935.
DATE-2008-MassierGS #design: Sizing Rules for Bipolar Analog Circuit Design (TM, HEG, US), pp. 140–145.
DATE-2008-NessL #design #fault tolerance #statistics: Guiding Circuit Level Fault-Tolerance Design with Statistical Methods (DCN, DJL), pp. 348–353.
DATE-2008-PradhanV #performance #synthesis #using: Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches (AP, RV), pp. 523–526.
DATE-2008-RoyKM #named: EPIC: Ending Piracy of Integrated Circuits (JAR, FK, ILM), pp. 1069–1074.
DATE-2008-SreedharSK #fault #modelling #on the #testing: On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits (AS, AS, SK), pp. 616–621.
DATE-2008-SterponeATG #design #fault tolerance #on the #safety: On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications (LS, MAA, JNT, HGM), pp. 336–341.
DATE-2008-VermaBI #design #latency #paradigm: Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design (AKV, PB, PI), pp. 1250–1255.
DATE-2008-WeinbergerBB #design #modelling #petri net #process #verification #workflow: Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits (KW, SB, RB), pp. 937–938.
DATE-2008-YoshidaF: Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits (HY, MF), pp. 1099–1102.
DATE-2008-ZhangPM #design #guidelines #logic: Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits (JZ, NP, SM), pp. 1009–1014.
ITiCSE-2008-Kurmas #automation #logic #performance #student #testing #using: Improving student performance using automated testing of simulated digital logic circuits (ZK), pp. 265–270.
STOC-2008-DvirSY #bound #trade-off: Hardness-randomness tradeoffs for bounded depth arithmetic circuits (ZD, AS, AY), pp. 741–748.
STOC-2008-Raz #bound: Elusive functions and lower bounds for arithmetic circuits (RR), pp. 711–720.
AFL-2008-Bartha #automaton #equivalence #simulation: Simulation equivalence of automata and circuits (MB), pp. 86–99.
ICALP-A-2008-HallgrenH #quantum: Superpolynomial Speedups Based on Almost Any Quantum Circuit (SH, AWH), pp. 782–795.
ICALP-A-2008-Saxena #bound #testing: Diagonal Circuit Identity Testing and Lower Bounds (NS), pp. 60–71.
ICALP-C-2008-KolesnikovS: Improved Garbled Circuit: Free XOR Gates and Applications (VK, TS), pp. 486–498.
SAC-2008-TarauL #synthesis: Revisiting exact combinational circuit synthesis (PT, BL), pp. 1758–1759.
CSL-2008-McKenzieTV: Extensional Uniformity for Boolean Circuits (PM, MT, HV), pp. 64–78.
ASE-2007-ZaraketAK #program analysis: Sequential circuits for program analysis (FAZ, AA, SK), pp. 114–123.
DAC-2007-AndrikosLPS: A Fully-Automated Desynchronization Flow for Synchronous Circuits (NA, LL, DP, CPS), pp. 982–985.
DAC-2007-BriskVIP #performance: Enhancing FPGA Performance for Arithmetic Circuits (PB, AKV, PI, HPA), pp. 334–337.
DAC-2007-CortadellaK #evaluation: Synchronous Elastic Circuits with Early Evaluation and Token Counterflow (JC, MK), pp. 416–419.
DAC-2007-CzajkowskiB #using: Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits (TSC, SDB), pp. 324–329.
DAC-2007-DadgourB #analysis #design #hybrid #power management: Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications (HFD, KB), pp. 306–311.
DAC-2007-HansonSSB #scalability: Nanometer Device Scaling in Subthreshold Circuits (SH, MS, DS, DB), pp. 700–705.
DAC-2007-KangKIAR #estimation #metric #online #reliability #using: Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement (KK, KK, AEI, MAA, KR), pp. 358–363.
DAC-2007-KangKR #design #power management #using: Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop (KK, KK, KR), pp. 934–939.
DAC-2007-KumarKS #synthesis: NBTI-Aware Synthesis of Digital Circuits (SVK, CHK, SSS), pp. 370–375.
DAC-2007-LiP #correlation #multi #parametricity #performance: Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits (XL, LTP), pp. 928–933.
DAC-2007-MaslovFM #empirical #interactive #optimisation #physics #quantum: Quantum Circuit Placement: Optimizing Qubit-to-qubit Interactions through Mapping Quantum Circuits into a Physical Experiment (DM, SMF, MM), pp. 962–965.
DAC-2007-McConaghyPGS #multi: Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies (TM, PP, GGEG, MS), pp. 944–947.
DAC-2007-Ozdal #clustering: Escape Routing For Dense Pin Clusters In Integrated Circuits (MMO), pp. 49–54.
DAC-2007-PatilDWM #automation #design: Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits (NP, JD, HSPW, SM), pp. 958–961.
DAC-2007-RastogiCK #on the: On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method (AR, WC, SK), pp. 712–715.
DAC-2007-SeokHSB #analysis #design #optimisation: Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design (MS, SH, DS, DB), pp. 694–699.
DAC-2007-SeomunKS: Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits (JS, JK, YS), pp. 103–106.
DAC-2007-SinghalBSLNC #analysis #modelling #simulation: Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation (RS, AB, ARS, FL, SRN, YC), pp. 823–828.
DAC-2007-VermaBI #composition #heuristic: Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits (AKV, PB, PI), pp. 404–409.
DAC-2007-WangYBVVLC #performance: The Impact of NBTI on the Performance of Combinational and Sequential Circuits (WW, SY, SB, RV, SBKV, FL, YC), pp. 364–369.
DAC-2007-YanTLM #higher-order #named #reduction: SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits (BY, SXDT, PL, BM), pp. 158–161.
DAC-2007-You: Engineering synthetic killer circuits in bacteria (LY), pp. 636–637.
DAC-2007-YuL #design: Design of Rotary Clock Based Circuits (ZY, XL), pp. 43–48.
DATE-2007-BorremansLWR #analysis #multi #using: Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis (JB, LDL, PW, YR), pp. 261–266.
DATE-2007-ChenZLC #analysis #performance #statistics: Fast statistical circuit analysis with finite-point based transistor model (MC, WZ, FL, YC), pp. 1391–1396.
DATE-2007-ChoudhuryM #analysis #logic #reliability #scalability: Accurate and scalable reliability analysis of logic circuits (MRC, KM), pp. 1454–1459.
DATE-2007-FanMTCH #correlation #order #reduction #statistics: Statistical model order reduction for interconnect circuits considering spatial correlations (JF, NM, SXDT, YC, XH), pp. 1508–1513.
DATE-2007-GaneshpureK #automation #fault #generative #interactive #multi: Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults (KPG, SK), pp. 540–545.
DATE-2007-GhoshBR #adaptation #scheduling #synthesis #using: Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling (SG, SB, KR), pp. 1532–1537.
DATE-2007-HashempourL #detection #fault #modelling: Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs (HH, FL), pp. 841–846.
DATE-2007-JayakumarK #algorithm: An algorithm to minimize leakage through simultaneous input vector control and circuit modification (NJ, SPK), pp. 618–623.
DATE-2007-LiuDSY #estimation #power management: Accurate temperature-dependent integrated circuit leakage power estimation is easy (YL, RPD, LS, HY), pp. 1526–1531.
DATE-2007-MangassarianVSNA #estimation #process #pseudo #satisfiability #using: Maximum circuit activity estimation using pseudo-boolean satisfiability (HM, AGV, SS, FNN, MSA), pp. 1538–1543.
DATE-2007-Miskov-ZivanovM #analysis #fault: Soft error rate analysis for sequential circuits (NMZ, DM), pp. 1436–1441.
DATE-2007-MondalRKRLVM #3d #robust: Thermally robust clocking schemes for 3D integrated circuits (MM, AJR, SK, TR, GML, NV, YM), pp. 1206–1211.
DATE-2007-MoonBP #approach #composition #equivalence: A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states (IHM, PB, CP), pp. 1170–1175.
DATE-2007-MuellerGS #design #polynomial #programming #trade-off #using: Trade-off design of analog circuits using goal attainment and “Wave Front” sequential quadratic programming (DM, HEG, US), pp. 75–80.
DATE-2007-NepalBMPZ #design #interactive #multi: Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits (KN, RIB, JLM, WRP, AZ), pp. 576–581.
DATE-2007-SchneiderSKW #interactive #simulation #statistics: Interactive presentation: Statistical simulation of high-frequency bipolar circuits (WS, MS, WK, HW), pp. 1397–1402.
DATE-2007-SingheeR #monte carlo #novel #performance #simulation #statistics: Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application (AS, RAR), pp. 1379–1384.
DATE-2007-TannirK #analysis #performance: Efficient nonlinear distortion analysis of RF circuits (DT, RK), pp. 255–260.
DATE-2007-WuLLH #named #robust #satisfiability: QuteSAT: a robust circuit-based SAT solver for complex circuit structure (CAW, THL, CCL, CYH), pp. 1313–1318.
DATE-2007-ZilicRK #specification: Reversible circuit technology mapping from non-reversible specifications (ZZ, KR, AK), pp. 558–563.
DATE-2007-ZjajoAG #interactive #monitoring #parametricity #process: Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits (AZ, MJBA, JPdG), pp. 1301–1306.
STOC-2007-Santhanam #bound: Circuit lower bounds for Merlin-Arthur classes (RS), pp. 275–283.
STOC-2007-Sherstov: Separating AC0 from depth-2 majority circuits (AAS), pp. 294–301.
STOC-2007-Shpilka #multi: Interpolation of depth-3 arithmetic circuits with two multiplication gates (AS), pp. 284–293.
ICSE-2007-ZaraketAK #analysis #relational: Sequential Circuits for Relational Analysis (FAZ, AA, SK), pp. 13–22.
CSL-2007-AehligB #logic: Propositional Logic for Circuit Classes (KA, AB), pp. 512–526.
ICLP-2007-TarauL #framework #logic programming #synthesis: A Logic Programming Framework for Combinational Circuit Synthesis (PT, BL), pp. 180–194.
SAT-2007-AudemardS #encoding: Circuit Based Encoding of CNF Formula (GA, LS), pp. 16–21.
SAT-2007-ManoliosV #performance: Efficient Circuit to CNF Conversion (PM, DV), pp. 4–9.
CASE-2006-ChenYY #algorithm #simulation: Backward-traversing Waveform Relaxation Algorithm for Circuit Simulation and Simulation on Demand (CJC, JLY, TNY), pp. 134–139.
DAC-2006-AmirtharajahWCSZ #energy: Circuits for energy harvesting sensor signal processing (RA, JW, JC, JS, BZ), pp. 639–644.
DAC-2006-BhardwajVGC #analysis #modelling #optimisation #process: Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits (SB, SBKV, PG, YC), pp. 791–796.
DAC-2006-ChangSC #design #evaluation #trade-off: Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs (KCC, JSS, TFC), pp. 143–148.
DAC-2006-HuaMSSMJD #3d: Exploring compromises among timing, power and temperature in three-dimensional integrated circuits (HH, CM, KS, AMS, SM, RJ, WRD), pp. 997–1002.
DAC-2006-JayakumarGGK #approach #design: A PLA based asynchronous micropipelining approach for subthreshold circuit design (NJ, RG, BG, SPK), pp. 419–424.
DAC-2006-KimSKE #design #physics #power management #standard: Physical design methodology of power gating circuits for standard-cell-based design (HOK, YS, HK, IE), pp. 109–112.
DAC-2006-MeiR #robust: A robust envelope following method applicable to both non-autonomous and oscillatory circuits (TM, JSR), pp. 1029–1034.
DAC-2006-Miskov-ZivanovM #fault #modelling #named #reduction: MARS-C: modeling and reduction of soft errors in combinational circuits (NMZ, DM), pp. 767–772.
DAC-2006-PakbazniaFP #analysis #concept: Charge recycling in MTCMOS circuits: concept and analysis (EP, FF, MP), pp. 97–102.
DAC-2006-PaulFOL #analysis #modelling #performance: Modeling and analysis of circuit performance of ballistic CNFET (BCP, SF, MO, TL), pp. 717–722.
DAC-2006-ShiMYH #simulation: Circuit simulation based obstacle-aware Steiner routing (YS, PM, HY, LH), pp. 385–388.
DAC-2006-TiwaryTR #design #generative: Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration (SKT, PKT, RAR), pp. 31–36.
DAC-2006-VermaI #architecture #automation #towards: Towards the automatic exploration of arithmetic-circuit architectures (AKV, PI), pp. 445–450.
DAC-2006-WaghmodeLS #scalability: Buffer insertion in large circuits with constructive solution search techniques (MW, ZL, WS), pp. 296–301.
DAC-2006-WeiD #composition #development #megamodelling: Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling (YW, AD), pp. 1023–1028.
DAC-2006-ZhangMBC #detection #representation #satisfiability #scalability #simulation #symmetry #using: Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability (JSZ, AM, RKB, MCJ), pp. 510–515.
DATE-2006-AbdollahiP #analysis #diagrams #quantum #synthesis #using: Analysis and synthesis of quantum circuits by using quantum decision diagrams (AA, MP), pp. 317–322.
DATE-2006-Albrecht #incremental #latency #performance #scalability #scheduling: Efficient incremental clock latency scheduling for large circuits (CA), pp. 1091–1096.
DATE-2006-BanerjeeRMB #fine-grained #logic #power management #synthesis #using: Low power synthesis of dynamic logic circuits using fine-grained clock gating (NB, KR, HMM, SB), pp. 862–867.
DATE-2006-BuhlerKBHSSPR #design #process: DFM/DFY design for manufacturability and yield — influence of process variations in digital, analog and mixed-signal circuit design (MB, JK, JB, JH, US, RS, MP, AR), pp. 387–392.
DATE-2006-ChenMBR #case study #design #power management: Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design (QC, SM, AB, KR), pp. 983–988.
DATE-2006-DuttA #incremental #locality #performance #using: Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations (SD, HA), pp. 768–773.
DATE-2006-FrehseKR #abstraction #refinement #using #verification: Verifying analog oscillator circuits using forward/backward abstraction refinement (GF, BHK, RAR), pp. 257–262.
DATE-2006-GandhiM #energy #multi #using: Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits (KRG, NRM), pp. 1001–1006.
DATE-2006-GillPW #analysis #fault #logic: Soft delay error analysis in logic circuits (BSG, CAP, FGW), pp. 47–52.
DATE-2006-GuptaJL #automaton #generative #quantum #testing: Test generation for combinational quantum cellular automata (QCA) circuits (PG, NKJ, LL), pp. 311–316.
DATE-2006-HosangadiFK #optimisation #using: Optimizing high speed arithmetic circuits using three-term extraction (AH, FF, RK), pp. 1294–1299.
DATE-2006-McConaghyG #canonical #modelling #performance: Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns (TM, GGEG), pp. 269–274.
DATE-2006-MohantyVK #optimisation: Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits (SPM, RV, EK), pp. 1191–1196.
DATE-2006-NepalBMPZ #design #fault #memory management: Designing MRF based error correcting circuits for memory elements (KN, RIB, JLM, WRP, AZ), pp. 792–793.
DATE-2006-PaulKKAR #design #estimation #performance #reliability: Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits (BCP, KK, HK, MAA, KR), pp. 780–785.
DATE-2006-RaoCBS #algorithm #fault #performance: An efficient static algorithm for computing the soft error rates of combinational circuits (RRR, KC, DB, DS), pp. 164–169.
DATE-2006-Ruiz-SautuaMMH #multi #optimisation #performance: Pre-synthesis optimization of multiplications to improve circuit performance (RRS, MCM, JMM, RH), pp. 1306–1311.
DATE-2006-SoffkeZMG #analysis #approach #combinator #statistics: A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits (OS, PZ, TM, MG), pp. 632–637.
DATE-2006-TanjiWKA #analysis #scalability #using: Large scale RLC circuit analysis using RLCG-MNA formulation (YT, TW, HK, HA), pp. 45–46.
DATE-2006-VandersteenBDR: Systematic stability-analysis method for analog circuits (GV, SB, PD, YR), pp. 150–155.
DATE-2006-YangV #analysis #evaluation #performance #synthesis: Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis (HY, RV), pp. 283–284.
DATE-2006-ZhangZD #modelling #named #parametricity #process: ALAMO: an improved alpha-space based methodology for modeling process parameter variations in analog circuits (HZ, YZ, AD), pp. 156–161.
DATE-DF-2006-BonfiniCMP #verification: A mixed-signal verification kit for verification of analogue-digital circuits (GB, MC, RM, EP), pp. 88–93.
DATE-DF-2006-LinHJC #optimisation #pattern matching #regular expression: Optimization of regular expression pattern matching circuits on FPGA (CHL, CTH, CPJ, SCC), pp. 12–17.
PEPM-2006-ThompsonM #partial evaluation: Bit-level partial evaluation of synchronous circuits (ST, AM), pp. 29–37.
STOC-2006-AngluinACW #injection #learning: Learning a circuit by injecting values (DA, JA, JC, YW), pp. 584–593.
ICALP-v1-2006-MagniezMMO #quantum #self: Self-testing of Quantum Circuits (FM, DM, MM, HO), pp. 72–83.
ICALP-v1-2006-UchizawaDM #complexity #energy: Energy Complexity and Entropy of Threshold Circuits (KU, RJD, WM), pp. 631–642.
SEKE-2006-LehmanW #convergence #problem #rule-based #simulation: A Rule-Based Expert System for the Diagnosis of Convergence Problems in Circuit Simulation (CWL, MJW), pp. 57–60.
SAT-2006-TangM #quantifier: Solving Quantified Boolean Formulas with Circuit Observability Don’t Cares (DT, SM), pp. 368–381.
DAC-2005-AbdollahiFP #effectiveness: An effective power mode transition technique in MTCMOS circuits (AA, FF, MP), pp. 37–42.
DAC-2005-AgarwalCBZ #analysis #optimisation #statistics #using: Circuit optimization using statistical static timing analysis (AA, KC, DB, VZ), pp. 321–324.
DAC-2005-AminID #approximate #using: Piece-wise approximations of RLCK circuit responses using moment matching (CSA, YII, FD), pp. 927–932.
DAC-2005-BeattieZDK #3d #distributed #modelling: Spatially distributed 3D circuit models (MWB, HZ, AD, BK), pp. 153–158.
DAC-2005-BhardwajV #random: Leakage minimization of nano-scale circuits in the presence of systematic and random variations (SB, SBKV), pp. 541–546.
DAC-2005-BhattacharyaJS #optimisation: Template-driven parasitic-aware optimization of analog integrated circuit layouts (SB, NJ, CJRS), pp. 644–647.
DAC-2005-CaoC #approach #modelling #performance #process #statistics #towards #variability: Mapping statistical process variations toward circuit performance variability: an analytical modeling approach (YC, LTC), pp. 658–663.
DAC-2005-DingV #megamodelling #performance: A combined feasibility and performance macromodel for analog circuits (MD, RV), pp. 63–68.
DAC-2005-GaoH #multi #reduction: Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages (FG, JPH), pp. 31–36.
DAC-2005-GielenME #modelling #performance #synthesis: Performance space modeling for hierarchical synthesis of analog integrated circuits (GGEG, TM, TE), pp. 881–886.
DAC-2005-Heidergott #design: SEU tolerant device, circuit and processor design (WH), pp. 5–10.
DAC-2005-JinS #performance: Prime clauses for fast enumeration of satisfying assignments to boolean circuits (HJ, FS), pp. 750–753.
DAC-2005-MonnetRL #evaluation #fault: Asynchronous circuits transient faults sensitivity evaluation (YM, MR, RL), pp. 863–868.
DAC-2005-NepalBMPZ #design #logic #probability: Designing logic circuits for probabilistic computation in the presence of noise (KN, RIB, JLM, WRP, AZ), pp. 485–490.
DAC-2005-TschanzBD: Variation-tolerant circuits: circuit solutions and techniques (JT, KAB, VD), pp. 762–763.
DAC-2005-Vasudevan #simulation: Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits (VV), pp. 397–402.
DAC-2005-WeiD #behaviour #development #megamodelling: Systematic development of analog circuit structural macromodels through behavioral model decoupling (YW, AD), pp. 57–62.
DAC-2005-ZhaoZD #constraints #robust: Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits (CZ, YZ, SD), pp. 190–195.
DATE-2005-BadaouiV #multi #performance #synthesis: Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis (RFB, RV), pp. 138–143.
DATE-2005-BiswasLBP #specification: Specification Test Compaction for Analog Circuits and MEMS (SB, PL, RD(B, LTP), pp. 164–169.
DATE-2005-BouesseRDG #formal method: DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement (GFB, MR, SD, FG), pp. 424–429.
DATE-2005-CabodiCNQ #bound #model checking #quantifier #set: Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking (GC, MC, SN, SQ), pp. 688–689.
DATE-2005-CarterOS #concurrent #fault #modelling #testing: Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown (JRC, SO, DJS), pp. 300–305.
DATE-2005-DhillonDC #analysis #optimisation: Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits (YSD, AUD, AC), pp. 288–293.
DATE-2005-DingV #approach #megamodelling #modelling #performance: A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling (MD, RV), pp. 1088–1089.
DATE-2005-EeckelaertMG #multi #performance #synthesis #using: Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces (TE, TM, GGEG), pp. 1070–1075.
DATE-2005-FuYM #satisfiability: Considering Circuit Observability Don’t Cares in CNF Satisfiability (ZF, YY, SM), pp. 1108–1113.
DATE-2005-GielenDCDJMV #design #question: Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? (GGEG, WD, PC, DD, EJ, KM, TV), pp. 36–42.
DATE-2005-IyerPC #constraints #learning #performance #theorem proving: Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver (MKI, GP, KTC), pp. 666–671.
DATE-2005-KumarTCJ #fault: Implicit and Exact Path Delay Fault Grading in Sequential Circuits (MMVK, ST, SC, RJ), pp. 990–995.
DATE-2005-LiS #performance #simulation: An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation (ZL, CJRS), pp. 752–757.
DATE-2005-LiuFYO #analysis #correlation #graph #modelling: Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing (FL, JJF, DVY, SO), pp. 126–131.
DATE-2005-MartinelliD #bound #composition #set: Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition (AM, ED), pp. 430–431.
DATE-2005-MaslovYMD #quantum #using: Quantum Circuit Simplification Using Templates (DM, CY, DMM, GWD), pp. 1208–1213.
DATE-2005-McConaghyEG #canonical #generative #named #programming #search-based: CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming (TM, TE, GGEG), pp. 1082–1087.
DATE-2005-MukhopadhyayBR #analysis #logic #modelling: Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits (SM, SB, KR), pp. 224–229.
DATE-2005-MullerTAL #design #multi #power management #top-down: Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit (PM, AT, SMA, YL), pp. 258–263.
DATE-2005-NeiroukhS #statistics #using: Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques (ON, XS), pp. 294–299.
DATE-2005-NoguchiN #monitoring #multi: On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits (KN, MN), pp. 146–151.
DATE-2005-PomeranzR05a #detection #fault #heuristic: The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits (IP, SMR), pp. 1008–1013.
DATE-2005-Ruiz-SautuaMMH #behaviour #performance #synthesis: Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis (RRS, MCM, JMM, RH), pp. 1252–1257.
DATE-2005-SandireddyA #detection #fault #multi: Diagnostic and Detection Fault Collapsing for Multiple Output Circuits (RKKRS, VDA), pp. 1014–1019.
DATE-2005-SavioliCCF #approach #fault: Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits (CES, CCC, JVC, ACdMF), pp. 174–175.
DATE-2005-SoensPWD #analysis #simulation: Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance (CS, GVdP, PW, SD), pp. 270–275.
DATE-2005-SomaniCP #contest #design #optimisation #search-based: Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits (AS, PPC, AP), pp. 1064–1069.
DATE-2005-SukhwaniPW #design #named #statistics: Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design (BBS, UP, JMW), pp. 758–763.
DATE-2005-TeslenkoD #algorithm #graph #performance: An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs (MT, ED), pp. 406–411.
DATE-2005-TiriV #constant #design #difference #logic #power management: Design Method for Constant Power Consumption of Differential Logic Circuits (KT, IV), pp. 628–633.
DATE-2005-VerleMAMA #optimisation #power management #protocol: Low Power Oriented CMOS Circuit Optimization Protocol (AV, XM, NA, PM, DA), pp. 640–645.
DATE-2005-YangHSP #logic #multi #quantum #synthesis #using: Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory (GY, WNNH, XS, MAP), pp. 434–435.
TACAS-2005-JinHS #analysis #performance: Efficient Conflict Analysis for Finding All Satisfying Assignments of a Boolean Circuit (HJ, HH, FS), pp. 287–300.
STOC-2005-DvirS #polynomial #query #testing: Locally decodable codes with 2 queries and polynomial identity testing for depth 3 circuits (ZD, AS), pp. 592–601.
STOC-2005-KouckyPT #bound: Bounded-depth circuits: separating wires from gates (MK, PP, DT), pp. 257–265.
CIAA-2005-Kresz #simulation: Simulation of Soliton Circuits (MK), pp. 347–348.
ICALP-2005-ChattopadhyayH #bound #composition #symmetry: Lower Bounds for Circuits with Few Modular and Symmetric Gates (AC, KAH), pp. 994–1005.
ICALP-2005-TessonT #communication #complexity #strict: Restricted Two-Variable Sentences, Circuits and Communication Complexity (PT, DT), pp. 526–538.
ICALP-2005-Valiant #artificial reality: Holographic Circuits (LGV), pp. 1–15.
SAC-2005-DalkilicS05a #classification #design #implementation #named: Circle: design and implementation of a classifier based on circuit minimization (MMD, AS), pp. 547–548.
SAT-J-2004-JacksonS05: Clause Form Conversions for Boolean Circuits (PJ, DS), pp. 183–198.
SAT-J-2004-TangYRM05 #algorithm #analysis #problem #quantifier #satisfiability: Analysis of Search Based Algorithms for Satisfiability of Propositional and Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems (DT, YY, DR, SM), pp. 292–305.
SAT-2005-Goldberg #equivalence #specification: Equivalence Checking of Circuits with Parameterized Specifications (EG), pp. 107–121.
DAC-2004-AntonelliCDHKKMN #automaton #clustering #modelling #problem: Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions (DAA, DZC, TJD, XSH, ABK, PMK, RCM, MTN), pp. 363–368.
DAC-2004-BasuLWMB #optimisation #power management: Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era (AB, SCL, VW, AM, KB), pp. 884–887.
DAC-2004-CaoK #logic #optimisation: Post-layout logic optimization of domino circuits (AC, CKK), pp. 820–825.
DAC-2004-DeleganesBGKSW #integer #logic: Low voltage swing logic circuits for a Pentium 4 processor integer core (DJD, MB, GG, KK, APS, SW), pp. 678–680.
DAC-2004-DingM #logic #novel: A novel technique to improve noise immunity of CMOS dynamic logic circuits (LD, PM), pp. 900–903.
DAC-2004-JeongN #detection #performance: Fast hazard detection in combinational circuits (CJ, SMN), pp. 592–595.
DAC-2004-KouroussisAN #power management #worst-case: Worst-case circuit delay taking into account power supply variations (DK, RA, FNN), pp. 652–657.
DAC-2004-KravetsK #optimisation: Implicit enumeration of structural changes in circuit optimization (VNK, PK), pp. 438–441.
DAC-2004-LeeDBABM #architecture #simulation: Circuit-aware architectural simulation (SL, SD, VB, TMA, DB, TNM), pp. 305–310.
DAC-2004-NookalaS: A method for correcting the functionality of a wire-pipelined circuit (VN, SSS), pp. 570–575.
DAC-2004-ParthasarathyICW #constraints #performance #theorem proving: An efficient finite-domain constraint solver for circuits (GP, MKI, KTC, LCW), pp. 212–217.
DAC-2004-SultaniaSS #trade-off: Tradeoffs between date oxide leakage and delay for dual Tox circuits (AKS, DS, SSS), pp. 761–766.
DAC-2004-TanGQ #analysis #approach #scalability: Hierarchical approach to exact symbolic analysis of large analog circuits (SXDT, WG, ZQ), pp. 860–863.
DAC-2004-XuPB #layout #named #optimisation: ORACLE: optimization with recourse of analog circuits including layout extraction (YX, LTP, SPB), pp. 151–154.
DAC-2004-ZhangDRRC #performance #synthesis #towards: A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits (GZ, EAD, RAR, RAR, LRC), pp. 155–158.
DAC-2004-ZhangHC #analysis #pipes and filters #statistics: Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining (LZ, YH, CCPC), pp. 904–907.
DAC-2004-ZhaoBD #analysis #scalability: A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits (CZ, XB, SD), pp. 894–899.
DATE-DF-2004-DiazS #physics: Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit (JCD, MS), pp. 134–139.
DATE-v1-2004-BoseN #array #memory management #modelling: Extraction of Schematic Array Models for Memory Circuits (SB, AN), pp. 570–577.
DATE-v1-2004-EfthymiouSE #automation #generative: Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits (AE, CPS, DAE), pp. 672–673.
DATE-v1-2004-GarciaMSN #scalability: A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit (JCG, JAMN, JS, HN), pp. 680–681.
DATE-v1-2004-HuangM #behaviour #identification #modelling: Identification and Modeling of Nonlinear Dynamic Behavior in Analog Circuits (XH, HAM), pp. 460–467.
DATE-v1-2004-KielyG #modelling #performance #using: Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines (TK, GGEG), pp. 448–453.
DATE-v1-2004-LeveugleA #fault #injection: Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow (RL, AA), pp. 590–595.
DATE-v1-2004-NathkeBHB #automation #behaviour #generative: Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques (LN, VB, LH, EB), pp. 442–447.
DATE-v1-2004-PomeranzVRS #detection #fault: Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis (IP, SV, SMR, BS), pp. 68–75.
DATE-v1-2004-RanjanVASVG #modelling #performance #synthesis #using: Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models (MR, WV, AA, HS, RV, GGEG), pp. 604–609.
DATE-v1-2004-RaudvereSSJ #abstraction #polynomial #verification: Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits (TR, AKS, IS, AJ), pp. 690–691.
DATE-v1-2004-TanQL #modelling #scalability #simulation: Hierarchical Modeling and Simulation of Large Analog Circuits (SXDT, ZQ, HL), pp. 740–741.
DATE-v2-2004-AbasRK #design #metric: Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit (MAA, GR, DJK), pp. 804–809.
DATE-v2-2004-AgarwalSYV #estimation: Accurate Estimation of Parasitic Capacitances in Analog Circuits (AA, HS, VY, RV), pp. 1364–1365.
DATE-v2-2004-BranoverKG #design: Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones (AB, RK, RG), pp. 870–877.
DATE-v2-2004-ChandraXSP #design #performance: An Interconnect Channel Design Methodology for High Performance Integrated Circuits (VC, AX, HS, LTP), pp. 1138–1143.
DATE-v2-2004-GlebovGZOPB #analysis: False-Noise Analysis for Domino Circuits (AG, SG, VZ, CO, RP, MRB), pp. 784–789.
DATE-v2-2004-GuptaJ #algorithm #architecture: An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology (PG, NKJ), pp. 974–979.
DATE-v2-2004-KarandikarS #implementation #performance: Fast Comparisons of Circuit Implementations (SKK, SSS), pp. 910–915.
DATE-v2-2004-MineKKWA #hybrid #linear #performance #reduction #simulation: Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits (TM, HK, AK, TW, HA), pp. 1327–1333.
DATE-v2-2004-ShendeMB #communication #quantum: Smaller Two-Qubit Circuits for Quantum Communication and Computation (VVS, ILM, SSB), pp. 980–987.
DATE-v2-2004-TirumurtiKSC #approach #modelling #power management: A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit (CT, SK, SSK, YSC), pp. 1078–1083.
DATE-v2-2004-ViamontesMH #quantum #simulation: High-Performance QuIDD-Based Simulation of Quantum Circuits (GFV, ILM, JPH), pp. 1354–1355.
DATE-v2-2004-WanS #compilation #multi #simulation: Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation (BW, CJRS), pp. 1310–1315.
DATE-v2-2004-ZhouZLLZC #analysis #using: Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method (XZ, DZ, JL, RL, XZ, CC), pp. 1322–1326.
SAS-2004-ThompsonM #abstract interpretation: Abstract Interpretation of Combinational Asynchronous Circuits (ST, AM), pp. 181–196.
LICS-2004-Terui #proving: Proof Nets and Boolean Circuits (KT), pp. 182–191.
SAT-2004-TangYRM #algorithm #analysis #problem #quantifier #satisfiability: Analysis of Search Based Algorithms for Satisfiability of Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems (DT, YY, DR, SM), pp. 214–223.
DAC-2003-AgarwalBZV #bound #refinement #statistics: Computation and Refinement of Statistical Bounds on Circuit Delay (AA, DB, VZ, SBKV), pp. 348–353.
DAC-2003-AgarwalSB03a #metric: Simple metrics for slew rate of RC circuits based on two circuit moments (KA, DS, DB), pp. 950–953.
DAC-2003-AminCI: Realizable RLCK circuit crunching (CSA, MHC, YII), pp. 226–231.
DAC-2003-BernardinisJS #performance #representation: Support vector machines for analog circuit performance representation (FDB, MIJ, ALSV), pp. 964–969.
DAC-2003-BorkarKNTKD #architecture #parametricity: Parameter variations and impact on circuits and microarchitecture (SB, TK, SN, JT, AK, VD), pp. 338–342.
DAC-2003-Edwards: Making cyclic circuits acyclic (SAE), pp. 159–162.
DAC-2003-Hayes #concept #named #quantum #tutorial: Tutorial: basic concepts in quantum circuits (JPH), p. 893.
DAC-2003-Hershenson #design #performance: Efficient description of the design space of analog circuits (MdMH), pp. 970–973.
DAC-2003-JessKNOV #parametricity #predict #statistics: Statistical timing for parametric yield prediction of digital integrated circuits (JAGJ, KK, SRN, RHJMO, CV), pp. 932–937.
DAC-2003-LiLXP #analysis #megamodelling: Analog and RF circuit macromodels for system-level analysis (XL, PL, YX, LTP), pp. 478–483.
DAC-2003-MantheLS #analysis: Symbolic analysis of analog circuits with hard nonlinearity (AM, ZL, CJRS), pp. 542–545.
DAC-2003-MukhopadhyayRR #estimation #logic #modelling: Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling (SM, AR, KR), pp. 169–174.
DAC-2003-RiedelB #synthesis: The synthesis of cyclic combinational circuits (MDR, JB), pp. 163–168.
DAC-2003-SaifhashemiP #abstraction #framework #modelling: Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction (AS, HP), pp. 330–333.
DAC-2003-StehrGA #analysis #bound #performance #trade-off: Performance trade-off analysis of analog circuits by normal-boundary intersection (GS, HEG, KA), pp. 958–963.
DAC-2003-Travaglione #algorithm #design #implementation #quantum: Designing and implementing small quantum circuits and algorithms (BT), pp. 894–899.
DAC-2003-VasilyevRW #algorithm #generative #modelling: A TBR-based trajectory piecewise-linear algorithm for generating accurate low-order models for nonlinear analog circuits and MEMS (DV, MR, JW), pp. 490–495.
DAC-2003-VasudevanR #using: Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique (VV, MR), pp. 538–541.
DAC-2003-YehM: Delay budgeting in sequential circuit with application on FPGA placement (CYY, MMS), pp. 202–207.
DAC-2003-YuH: Vector potential equivalent circuit based on PEEC inversion (HY, LH), pp. 718–723.
DATE-2003-ChoiR #logic: A New Crosstalk Noise Model for DOMINO Logic Circuits (SHC, KR), pp. 11112–11113.
DATE-2003-CorsiMM #approach #classification #pseudo #random testing #testing: An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing Scheme (FC, CM, GM), pp. 11178–11179.
DATE-2003-DoboliGD #clustering #modelling #network #using: Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering (SD, GG, AD), pp. 11098–11099.
DATE-2003-DobrovolnyVWD #analysis #modelling: Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits (PD, GV, PW, SD), pp. 10624–10629.
DATE-2003-FreitasO #equation #estimation: Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits: An Application in Power Estimation (ATF, ALO), pp. 10764–10769.
DATE-2003-GouraryRUZGM #approach #approximate: Approximation Approach for Timing Jitter Characterization in Circuit Simulators (MMG, SGR, SLU, MMZ, KKG, BJM), pp. 10156–10161.
DATE-2003-GrundmannGK #challenge #design #framework: Circuit and Platform Design Challenges in Technologies beyond 90nm (BG, RG, SK), pp. 10044–10049.
DATE-2003-IchiharaI #fault #generative #testing: Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG (HI, TI), pp. 11180–11181.
DATE-2003-LuWCH #correlation #learning #satisfiability: A Circuit SAT Solver With Signal Correlation Guided Learning (FL, LCW, KTC, RCYH), pp. 10892–10897.
DATE-2003-MadalinskiBKY #design #visualisation: Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design (AM, AVB, VK, AY), pp. 10926–10931.
DATE-2003-MantheLSM #analysis: Symbolic Analysis of Nonlinear Analog Circuits (AM, ZL, CJRS, KM), pp. 11108–11109.
DATE-2003-NummerS #pipes and filters #testing: DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers (MN, MS), pp. 10212–10217.
DATE-2003-PomeranzR #approach #generative #testing: A New Approach to Test Generation and Test Compaction for Scan Circuits (IP, SMR), pp. 11000–11005.
DATE-2003-SmedtG #bound #design #named: HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits (BDS, GGEG), pp. 10256–10263.
DATE-2003-SokolovBY #optimisation: STG Optimisation in the Direct Mapping of Asynchronous Circuits (DS, AVB, AY), pp. 10932–10939.
DATE-2003-XuLLP #megamodelling: Noise Macromodel for Radio Frequency Integrated Circuits (YX, XL, PL, LTP), pp. 10150–10155.
DATE-2003-Zhou #verification: Timing Verification with Crosstalk for Transparently Latched Circuits (HZ), pp. 10056–10061.
STOC-2003-KabanetsI #bound #polynomial #proving #testing: Derandomizing polynomial identity tests means proving circuit lower bounds (VK, RI), pp. 355–364.
ICALP-2003-Schnoebelen #model checking: Oracle Circuits for Branching-Time Model Checking (PS), pp. 790–801.
SAC-2003-GassendCDD #authentication: Delay-Based Circuit Authentication and Applications (BG, DEC, MvD, SD), pp. 294–301.
SAT-2003-BroeringL #algorithm #satisfiability: Width-Based Algorithms for SAT and CIRCUIT-SAT: (Extended Abstract) (EB, SVL), pp. 162–171.
DAC-2002-AnisMEA #automation #clustering #performance #power management #reduction #using: Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique (MA, MM, MIE, SA), pp. 480–485.
DAC-2002-BadarogluTDWMVG #optimisation #reduction #using: Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients (MB, KT, SD, PW, HDM, IV, GGEG), pp. 399–404.
DAC-2002-BaiVS #optimisation: Uncertainty-aware circuit optimization (XB, CV, PNS), pp. 58–63.
DAC-2002-ChangC #implementation #self #verification: Self-referential verification of gate-level implementations of arithmetic circuits (YTC, KTC), pp. 311–316.
DAC-2002-DaemsGS #modelling #performance: An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits (WD, GGEG, WMCS), pp. 431–436.
DAC-2002-FoltinFT #abstraction #concept #independence #modelling #performance: Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency (MF, BF, ST), pp. 158–163.
DAC-2002-GanaiAGZM #algorithm #satisfiability: Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver (MKG, PA, AG, LZ, SM), pp. 747–750.
DAC-2002-Higuchi #detection #multi #scalability: An implication-based method to detect multi-cycle paths in large sequential circuits (HH), pp. 164–169.
DAC-2002-IonescuDMBG #hybrid #towards: Few electron devices: towards hybrid CMOS-SET integrated circuits (AMI, MJD, SM, KB, JG), pp. 88–93.
DAC-2002-IwamaKY #design #quantum: Transformation rules for designing CNOT-based quantum circuits (KI, YK, SY), pp. 419–424.
DAC-2002-JollyPM #automation #equivalence: Automated equivalence checking of switch level circuits (SJ, ANP, TM), pp. 299–304.
DAC-2002-KondratyevL #design #tool support: Design of asynchronous circuits by synchronous CAD tools (AK, KL), pp. 411–414.
DAC-2002-LiuSRC #data mining #design #megamodelling #mining #scalability: Remembrance of circuits past: macromodeling by data mining in large analog design spaces (HL, AS, RAR, LRC), pp. 437–442.
DAC-2002-MartelDAWA #logic: Carbon nanotube field-effect transistors and logic circuits (RM, VD, JA, SJW, PA), pp. 94–98.
DAC-2002-MoB: River PLAs: a regular circuit structure (FM, RKB), pp. 201–206.
DAC-2002-Perrott #behaviour #performance #simulation: Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits (MHP), pp. 498–503.
DAC-2002-Sotiriou #implementation #using: Implementing asynchronous circuits using a conventional EDA tool-flow (CPS), pp. 415–418.
DAC-2002-UmK #synthesis: Layout-aware synthesis of arithmetic circuits (JU, TK), pp. 207–212.
DATE-2002-AbabeiB #clustering #statistics: Statistical Timing Driven Partitioning for VLSI Circuits (CA, KB), p. 1109.
DATE-2002-BerkelaarE #effectiveness #performance: Efficient and Effective Redundancy Removal for Million-Gate Circuits (MRCMB, KvE), p. 1088.
DATE-2002-Bose #automation #modelling: Automated Modeling of Custom Digital Circuits for Test (SB), pp. 954–961.
DATE-2002-CathelinSBLC: Substrate Parasitic Extraction for RF Integrated Circuits (AC, DS, DB, YL, FC), p. 1107.
DATE-2002-DaemsGS #approach #linear #performance: A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics (WD, GGEG, WMCS), pp. 268–273.
DATE-2002-DingM #performance: Optimal Transistor Tapering for High-Speed CMOS Circuits (LD, PM), pp. 708–713.
DATE-2002-Hoffmann #design #generative #testing: A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits (CH), pp. 197–204.
DATE-2002-JerkeL #analysis #verification: Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits (GJ, JL), pp. 464–469.
DATE-2002-LevantR #design: An EMC-Compliant Design Method of High-Density Integrated Circuits (JLL, MR), p. 1115.
DATE-2002-LinLC #feedback #performance: An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits (JWL, CLL, JEC), p. 1119.
DATE-2002-MolinaMH #independence #multi: Multiple-Precision Circuits Allocation Independent of Data-Objects Length (MCM, JMM, RH), pp. 909–913.
DATE-2002-MukherjeeWCM #component: Sizing Power/Ground Meshes for Clocking and Computing Circuit Components (AM, KW, LHC, MMS), pp. 176–183.
DATE-2002-PenaCSP #case study #verification: A Case Study for the Verification of Complex Timed Circuits: IPCMOS (MAP, JC, ABS, EP), pp. 44–51.
DATE-2002-PenzesM #energy #estimation: An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor (PIP, AJM), pp. 640–647.
DATE-2002-PoppOHB #analysis #automation #parametricity: Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits (RP, JO, LH, EB), pp. 274–278.
DATE-2002-PronathGA #design #fault #float: A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits (MP, HEG, KA), pp. 78–83.
DATE-2002-SchwenckerSPG #adaptation #parametricity #set #using #worst-case: Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets (RS, FS, MP, HEG), pp. 581–585.
DATE-2002-StanP: The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits (MRS, AP), p. 1106.
DATE-2002-ThielenV #performance #simulation: Fast Method to Include Parasitic Coupling in Circuit Simulations (BLAVT, GAEV), pp. 1033–1037.
DATE-2002-ThorntonFRT #evaluation #self: Generalized Early Evaluation in Self-Timed Circuits (MAT, KF, RBR, CT), pp. 255–259.
DATE-2002-TugsinavisutB #pipes and filters: Control Circuit Templates for Asynchronous Bundled-Data Pipelines (ST, PAB), p. 1098.
DATE-2002-VoorakaranamCC #agile #framework #testing: A Signature Test Framework for Rapid Production Testing of RF Circuits (RV, SC, AC), pp. 186–191.
DATE-2002-ZhengPBK #analysis #modelling #scalability: Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses (HZ, LTP, MWB, BK), pp. 628–633.
CIAA-2002-BrzozowskiG #algebra #simulation: Simulation of Gate Circuits in the Algebra of Transients (JAB, MG), pp. 57–66.
CIAA-2002-GheorghiuB #algebra: Feedback-Free Circuits in the Algebra of Transients (MG, JAB), pp. 106–116.
SAC-2002-CornoRS #algorithm: An evolutionary algorithm for reducing integrated-circuit test application time (FC, MSR, GS), pp. 608–612.
DAC-2001-BaiBH #analysis #power management: Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits (GB, SB, INH), pp. 295–300.
DAC-2001-KimCL #estimation #logic: A Static Estimation Technique of Power Sensitivity in Logic Circuits (TK, KSC, CLL), pp. 215–219.
DAC-2001-KuehlmannGP #reasoning: Circuit-based Boolean Reasoning (AK, MKG, VP), pp. 232–237.
DAC-2001-McDonaldB #analysis #simulation #using: Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis (CBM, REB), pp. 283–288.
DAC-2001-Pomeranz #random #testing: Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits (IP), pp. 145–150.
DAC-2001-PomeranzR #approach #testing: An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing (IP, SMR), pp. 156–161.
DAC-2001-RaahemifarA #detection #fault: Fault Characterizations and Design-for-Testability Technique for Detecting IDDQ Faults in CMOS/BiCMOS Circuits (KR, MA), pp. 313–316.
DAC-2001-SavojR #communication #design: Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems (JS, BR), pp. 121–126.
DAC-2001-SinghMM #latency: Latency and Latch Count Minimization in Wave Steered Circuits (AS, AM, MMS), pp. 383–388.
DAC-2001-TanS #modelling #network #optimisation #performance: Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling (SXDT, CJRS), pp. 550–554.
DAC-2001-VerhaegenG #analysis #linear #performance #scalability: Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits (WV, GGEG), pp. 139–144.
DAC-2001-YuYW #representation #synthesis #using: Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path Circuits (ZY, MLY, ANWJ), pp. 456–461.
DATE-2001-BadarogluHGDMGEB #generative #multi #scalability #simulation: High-level simulation of substrate noise generation from large digital circuits with multiple supplies (MB, MvH, VG, SD, HDM, GGEG, ME, IB), pp. 326–330.
DATE-2001-Burdiek #generative #programming #using: Generation of optimum test stimuli for nonlinear analog circuits using nonlinear — programming and time-domain sensitivities (BB), pp. 603–609.
DATE-2001-CherubalC #generative #parametricity #testing: Test generation based diagnosis of device parameters for analog circuits (SC, AC), pp. 596–602.
DATE-2001-CheungWC #clustering #logic #using: Further improve circuit partitioning using GBAW logic perturbation techniques (CCC, YLW, DIC), pp. 233–239.
DATE-2001-GarnicaLH #power management #pseudo: A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits (OG, JL, RH), p. 810.
DATE-2001-IrionKVW #clustering #logic #performance #synthesis: Circuit partitioning for efficient logic BIST synthesis (AI, GK, HPEV, HJW), pp. 86–91.
DATE-2001-KralicekJG #analysis #modelling: Modeling electromagnetic emission of integrated circuits for system analysis (PK, WJ, HG), pp. 336–340.
DATE-2001-LienigJA #approach #named: AnalogRouter: a new approach of current-driven routing for analog circuits (JL, GJ, TA), p. 819.
DATE-2001-NaiduJ #power management: Minimizing stand-by leakage power in static CMOS circuits (SRN, ETAFJ), pp. 370–376.
DATE-2001-OlbrichRB #algorithm #analysis #classification: An improved hierarchical classification algorithm for structural analysis of integrated circuits (MO, AR, EB), p. 807.
DATE-2001-UbarJP #diagrams #simulation: Timing simulation of digital circuits with binary decision diagrams (RU, AJ, ZP), pp. 460–466.
DATE-2001-WambacqVPREYLD: CAD for RF circuits (PW, GV, JRP, JSR, WE, BY, DEL, AD), pp. 520–529.
DATE-2001-WernerGWR: Crosstalk noise in future digital CMOS circuits (CW, RG, AW, UR), pp. 331–335.
STOC-2001-LachishR #bound: Explicit lower bound of 4.5n — o(n) for boolena circuits (OL, RR), pp. 399–408.
STOC-2001-RazS #bound #matrix: Lower bounds for matrix product, in bounded depth circuits with arbitrary gates (RR, AS), pp. 409–418.
STOC-2001-Trakhtenbrot #automaton: Automata, circuits and hybrids: facets of continuous time (BAT), pp. 754–755.
ICALP-2001-Trakhtenbrot #automaton: Automata, Circuits, and Hybrids: Facets of Continuous Time (BAT), pp. 4–23.
SAC-2001-CornoRS #architecture #effectiveness #evolution: Evolving effective CA/CSTP: BIST architectures for sequential circuits (FC, MSR, GS), pp. 345–350.
HPCA-2001-YangPFRV #approach #architecture: An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches (SHY, MDP, BF, KR, TNV), pp. 147–157.
CAV-2001-ZhengMM #abstraction #automation #verification: Automatic Abstraction for Verification of Timed Circuits and Systems (HZ, EM, CJM), pp. 182–193.
DAC-2000-FotyB #design #modelling #tutorial: MOSFET modeling and circuit design: re-establishing a lost connection (tutorial) (DF, DB), p. 560.
DAC-2000-GaurdianiSMSC #bound #component #constant #simulation #statistics: An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects (CG, SS, PM, PS, DC), pp. 15–18.
DAC-2000-GhoshF #automation #diagrams #functional #generative #using: Automatic test pattern generation for functional RTL circuits using assignment decision diagrams (IG, MF), pp. 43–48.
DAC-2000-MehrotraSBCVN #modelling #performance: A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance (VM, SLS, DSB, AC, RV, SRN), pp. 172–175.
DAC-2000-NemaniT #design: Macro-driven circuit design methodology for high-performance datapaths (MN, VT), pp. 661–666.
DAC-2000-PiS #analysis #approach #diagrams #multi: Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits (TP, CJRS), pp. 19–22.
DAC-2000-Sheehan #predict: Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments (BNS), pp. 532–535.
DAC-2000-ShepardK #analysis: Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology (KLS, DJK), pp. 239–242.
DAC-2000-SomasekharCRYD #analysis: Dynamic noise analysis in precharge-evaluate circuits (DS, SHC, KR, YY, VD), p. 243.
DAC-2000-WangN #analysis #linear #multi #order: Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources (JMW, TVN), pp. 247–252.
DAC-2000-YangP #multi #performance #simulation: A multi-interval Chebyshev collocation method for efficient high-accuracy RF circuit simulation (BY, JRP), pp. 178–183.
DAC-2000-YouVMX #approach #design #multi: A practical approach to parasitic extraction for design of multimillion-transistor integrated circuits (EY, LV, JM, WX), pp. 69–74.
DATE-2000-CarroSNJF #component: Non-Linear Components for Mixed Circuits Analog Front-End (LC, AAdSJ, MN, GPJ, DTF), pp. 544–549.
DATE-2000-DemirF #evaluation #modelling #performance #probability: Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits (AD, PF), pp. 340–344.
DATE-2000-DessoukyLP #performance #synthesis: Layout-Oriented Synthesis of High Performance Analog Circuits (MD, MML, JP), pp. 53–57.
DATE-2000-FrohlichGF #clustering #parallel #simulation: A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level (NF, VG, JF), pp. 679–684.
DATE-2000-GuerraRFR #analysis #approach #scalability: A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits (OG, ER, FVF, ÁRV), pp. 48–52.
DATE-2000-HoffmannK #fault #multi: Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits (DWH, TK), p. 758.
DATE-2000-NicoliciA #clustering #multi #power management: Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits (NN, BMAH), pp. 715–722.
DATE-2000-NooshabadiMNSS: A Single Phase Latch for High Speed GaAs Domino Circuits (SN, JAMN, AN, RS, JS), p. 760.
DATE-2000-PaulusKT #constraints #optimisation: Area Optimization of Analog Circuits Considering Matching Constraints (CP, UK, RT), p. 738.
DATE-2000-PomeranzR #generative #sequence #testing: Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits (IP, SMR), pp. 298–304.
DATE-2000-PomeranzR00a #functional #generative #testing: Functional Test Generation for Full Scan Circuits (IP, SMR), pp. 396–401.
DATE-2000-SchollB #generative #logic #multi #on the: On the Generation of Multiplexer Circuits for Pass Transistor Logic (CS, BB), pp. 372–378.
DATE-2000-SchonherrS #algorithm #automation #equivalence: Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level (JS, BS), p. 759.
DATE-2000-SchwenckerSGA #automation #bound #design: The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits (RS, FS, HEG, KA), pp. 42–47.
DATE-2000-Sheehan #predict: Predicting Coupled Noise in RC Circuits (BNS), pp. 517–521.
DATE-2000-VardanianM #concurrent #detection #fault: Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit Under Check (VAV, LBM), p. 762.
DATE-2000-WambacqDDEB #communication #modelling: Compact Modeling of Nonlinear Distortion in Analog Communication Circuits (PW, PD, SD, ME, IB), pp. 350–354.
STOC-2000-KabanetsC #problem: Circuit minimization problem (VK, JyC), pp. 73–79.
CAV-2000-HeymanGGS #analysis #parallel #reachability #scalability: Achieving Scalability in Parallel Reachability Analysis of Very Large Circuits (TH, DG, OG, AS), pp. 20–35.
CAV-2000-KukulaS: Building Circuits from Relations (JHK, TRS), pp. 113–123.
CAV-2000-Yoneda #named #verification: VINAS-P: A Tool for Trace Theoretic Verification of Timed Asynchronous Circuits (TY), pp. 572–575.
CL-2000-AzevedoB #constraints #modelling #problem #set: Modelling Digital Circuits Problems with Set Constraints (FA, PB), pp. 414–428.
CL-2000-JunttilaN #performance #satisfiability #towards: Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking (TAJ, IN), pp. 553–567.
DAC-1999-BertaccoDQ #simulation: Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits (VB, MD, SQ), pp. 391–396.
DAC-1999-ChinosiZG #clustering #parallel #simulation: Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning (MC, RZ, CG), pp. 562–567.
DAC-1999-CongLW #clustering #optimisation #performance: Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization (JC, HL, CW), pp. 460–465.
DAC-1999-ConnEMOSVW #optimisation #using: Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation (ARC, IME, WWM, PRO, PNS, CV, CBW), pp. 452–459.
DAC-1999-DaemsGS #analysis #complexity #reduction: Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits (WD, GGEG, WMCS), pp. 958–963.
DAC-1999-FengPNKW #approach #performance: Efficient Computation of Quasi-Periodic Circuit Operating Conditions via a Mixed Frequency/Time Approach (DF, JRP, KN, KSK, JW), pp. 635–640.
DAC-1999-GunupudiN #using: Model-Reduction of Nonlinear Circuits Using Krylov-Space Techniques (PKG, MSN), pp. 13–16.
DAC-1999-GuoRP #generative #named #using: Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction (RG, SMR, IP), pp. 653–659.
DAC-1999-HershensonMBL #geometry #optimisation #programming: Optimization of Inductor Circuits via Geometric Programming (MdMH, SSM, SPB, THL), pp. 994–998.
DAC-1999-HuangL #embedded #named: ICEBERG: An Embedded In-Circuit Emulator Synthesizer for Microcontrollers (IJH, TAL), pp. 580–585.
DAC-1999-IsmailF: Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits (YII, EGF), pp. 721–724.
DAC-1999-KamonMMSW #3d #analysis #modelling: Interconnect Analysis: From 3-D Structures to Circuit Models (MK, NAM, YM, LMS, JW), pp. 910–914.
DAC-1999-LiTRK #modelling #simulation: Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation (TL, CHT, ER, SMK), pp. 549–554.
DAC-1999-Oliveira #design #robust: Robust Techniques for Watermarking Sequential Circuit Designs (ALO), pp. 837–842.
DAC-1999-PatraN #automation #power management #synthesis: Automated Phase Assignment for the Synthesis of Low Power Domino Circuits (PP, UN), pp. 379–384.
DAC-1999-PomeranzR #generative #sequence #testing: Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences (IP, SMR), pp. 754–759.
DAC-1999-Sheehan #equation #named #order #performance #reduction #using: ENOR: Model Order Reduction of RLC Circuits Using Nodal Equations for Efficient Factorization (BNS), pp. 17–21.
DAC-1999-SirichotiyakulEOZDPB #power management: Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing (SS, TE, CO, JZ, AD, RP, DB), pp. 436–441.
DAC-1999-StevensRBCGKR #performance: CAD Directions for High Performance Asynchronous Circuits (KSS, SR, SMB, JC, RG, MK, MR), pp. 116–121.
DAC-1999-SundararajanP #power management #synthesis #using: Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages (VS, KKP), pp. 72–75.
DAC-1999-WeiCRYD #design #power management: Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications (LW, ZC, KR, YY, VD), pp. 430–435.
DATE-1999-AntakiSXA #design #testing: Design For Testability Method for CML Digital Circuits (BA, YS, NX, SA), pp. 360–367.
DATE-1999-CornoRS #algorithm #approximate #equivalence #search-based #verification: Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms (FC, MSR, GS), pp. 754–755.
DATE-1999-CotaCL #adaptation #fault #linear #using: A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester (ÉFC, LC, ML), pp. 184–188.
DATE-1999-Dewilde #design #scalability #source code: Large European Programs in Microelectronic System and Circuit Design (PD), p. 734–?.
DATE-1999-EcklL #multi: Retiming Sequential Circuits with Multiple Register Classes (KE, CL), p. 650–?.
DATE-1999-FavalliM #design #functional #on the #self: On the Design of Self-Checking Functional Units Based on Shannon Circuits (MF, CM), pp. 368–375.
DATE-1999-GomesC #testing #using: Minimal Length Diagnostic Tests for Analog Circuits using Test History (AVG, AC), pp. 189–194.
DATE-1999-Hsiao #estimation #optimisation #scalability #search-based #using: Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits (MSH), p. 175–?.
DATE-1999-HuhnSKL #verification: Verifying Imprecisely Working Arithmetic Circuits (MH, KS, TK, GL), p. 65–?.
DATE-1999-KonijnenburgLG #generative #identification #testing: Illegal State Space Identification for Sequential Circuit Test Generation (MHK, JTvdL, AJvdG), pp. 741–746.
DATE-1999-LechnerFRH #automation #performance #self: A Digital Partial Built-In Self-Test for a High Performance Automatic Gain Control Circuit (AL, JF, AR, BH), pp. 232–238.
DATE-1999-LiuPF: Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits (XL, MCP, EGF), pp. 643–649.
DATE-1999-MaamarR #adaptation #named #testing: ADOLT — An ADaptable On — Line Testing Scheme for VLSI Circuits (AM, GR), pp. 770–771.
DATE-1999-Nunez-AldanaV #effectiveness #performance #synthesis: An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis (ANA, RV), pp. 406–411.
DATE-1999-PapachristouA #design #distributed: A Method of Distributed Controller Design for RTL Circuits (CAP, YA), pp. 774–775.
DATE-1999-RaikU #diagrams #generative #modelling #testing #using: Sequential Circuit Test Generation Using Decision Diagram Models (JR, RU), pp. 736–740.
DATE-1999-RanjanSSB #using #verification: Using Combinational Verification for Sequential Circuits (RKR, VS, FS, RKB), pp. 138–144.
DATE-1999-RayaneVN #detection #embedded: A One-Bit-Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection (IR, JVM, MN), p. 792–?.
DATE-1999-ReutterR #design #performance #reuse: An Efficient Reuse System for Digital Circuit Design (AR, WR), pp. 38–43.
DATE-1999-RibasC #clustering #modelling: Digital MOS Circuit Partitioning with Symbolic Modeling (LR, JC), pp. 503–508.
DATE-1999-SchwenckerEGA #automation #constraints: Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints (RS, JE, HEG, KA), pp. 323–327.
DATE-1999-SilvaSM #algorithm #satisfiability: Algorithms for Solving Boolean Satisfiability in Combinational Circuits (LGeS, LMS, JPMS), pp. 526–530.
DATE-1999-TanS #diagrams #scalability #using: Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams (XDT, CJRS), pp. 448–453.
DATE-1999-YangZ #fault #performance #robust #simulation: Fast, Robust DC and Transient Fault Simulation for Nonlinear Analog Circuits (ZRY, MZ), pp. 244–248.
ICALP-1999-AllenderABDL #bound: Bounded Depth Arithmetic Circuits: Counting and Closure (EA, AA, DAMB, SD, HL), pp. 149–158.
WIA-1999-SeuringG #automaton: A Structural Method for Output Compaction of Sequential Automata Implemented as Circuits (MS, MG), pp. 158–163.
DAC-1998-CuletuAM: A Practical Repeater Insertion Method in High Speed VLSI Circuits (JC, CA, JM), pp. 392–395.
DAC-1998-El-MalehKR #learning #performance: A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance (AHEM, MK, JR), pp. 625–631.
DAC-1998-HuangCCL #design #fault: Fault-Simulation Based Design Error Diagnosis for Sequential Circuits (SYH, KTC, KCC, JYJL), pp. 632–637.
DAC-1998-KwakP #estimation #fault #logic #statistics: An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits (BK, ESP), pp. 690–693.
DAC-1998-LakshminarayanaJ98a #behaviour #power management #synthesis: Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions (GL, NKJ), pp. 439–444.
DAC-1998-LiK #layout #verification: Layout Extraction and Verification Methodology CMOS I/O Circuits (TL, SMK), pp. 291–296.
DAC-1998-LiuC: Extending Moment Computation to 2-Port Circuit Representations (FJL, CKC), pp. 473–476.
DAC-1998-LokanathanB #multi #optimisation #process: Process Multi-Circuit Optimization (ANL, JBB), pp. 382–387.
DAC-1998-NemaniN #estimation #perspective: Delay Estimation VLSI Circuits from a High-Level View (MN, FNN), pp. 591–594.
DAC-1998-OrshanskyCH #performance #simulation #statistics: A Statistical Performance Simulation Methodology for VLSI Circuits (MO, JCC, CH), pp. 402–407.
DAC-1998-Shepard #design: Design Methodologies for Noise in Digital Integrated Circuits (KLS), pp. 94–99.
DAC-1998-WeiCJRD #design #optimisation #performance: Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits (LW, ZC, MJ, KR, VD), pp. 489–494.
DAC-1998-Yuan #modelling #network #simulation: Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printed Circuit Boards (FYY), pp. 421–426.
DATE-1998-Catthoor #architecture #design #energy #performance: Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit Technology versus Design Methodology Solutions (FC), pp. 709–714.
DATE-1998-Cheng #multi #on the: On Removing Multiple Redundancies in Combinational Circuits (DIC), pp. 738–742.
DATE-1998-DroegeTH #named: EASY — a System for Computer-Aided Examination of Analog Circuits (GD, MT, EHH), pp. 644–648.
DATE-1998-EckmuellerGG: Hierarchical Characterization of Analog Integrated CMOS Circuits (JE, MG, HEG), pp. 636–643.
DATE-1998-FreundF #approximate #linear #modelling #multi #scalability #using: Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation (RWF, PF), pp. 530–537.
DATE-1998-GhoshKBH #benchmark #equivalence #invariant #metric #synthesis: Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking (DG, NK, FB, JEHI), pp. 656–663.
DATE-1998-GuoPR #sequence #testing: Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration (RG, IP, SMR), pp. 583–587.
DATE-1998-HedrichB #approach #formal method #linear #parametricity #verification: A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances (LH, EB), pp. 649–654.
DATE-1998-HsiaoC #performance #sequence: State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits (MSH, STC), pp. 577–582.
DATE-1998-JiangC #approximate #estimation: Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits (YMJ, KTC), pp. 698–702.
DATE-1998-KhouriLJ #control flow #named #power management #synthesis: IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits (KSK, GL, NKJ), pp. 848–854.
DATE-1998-KimuraI #analysis #design: A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator (HK, NI), pp. 951–952.
DATE-1998-KoegstGCW #analysis #design #reuse: A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits (MK, DG, PC, MGW), pp. 292–296.
DATE-1998-MaheshwariS #performance #scalability: Efficient Minarea Retiming of Large Level-Clocked Circuits (NM, SSS), pp. 840–845.
DATE-1998-PomeranzR98a #using: Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines (IP, SMR), pp. 983–984.
DATE-1998-PrietoRGPHR #approach #design #fault #layout #predict #testing: An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits (JAP, AR, IAG, EJP, JLH, AMDR), pp. 905–909.
DATE-1998-PullelaPDV: CMOS Combinational Circuit Sizing by Stage-wise Tapering (SP, RP, AD, GV), pp. 985–986.
DATE-1998-RenovellAB #implementation #multi: Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits (MR, FA, YB), pp. 815–821.
DATE-1998-RibasC #equivalence #incremental #on the #reuse #simulation #verification: On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits (LR, JC), pp. 624–629.
DATE-1998-RudnickVECPR #generative #performance #testing #using: Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques (EMR, RV, AE, FC, PP, MSR), pp. 570–576.
DATE-1998-TianS #fault #performance #simulation: Efficient DC Fault Simulation of Nonlinear Analog Circuits (MWT, CJRS), pp. 899–904.
DATE-1998-Velasco-MedinaCN #detection #fault #injection #linear #using: Fault Detection for Linear Analog Circuits Using Current Injection (JVM, TC, MN), pp. 987–988.
DATE-1998-WangV #data-driven #optimisation: Data Driven Power Optimization of Sequential Circuits (QW, SBKV), pp. 686–691.
STOC-1998-AharonovKN #quantum: Quantum Circuits with Mixed States (DA, AK, NN), pp. 20–30.
STOC-1998-ColeMHMRSSV #multi #network #protocol #random: Randomized Protocols for Low Congestion Circuit Routing in Multistage Interconnection Networks (RC, BMM, FMadH, MM, AWR, KS, RKS, BV), pp. 378–388.
STOC-1998-GrigorievK #bound #exponential: An Exponential Lower Bound for Depth 3 Arithmetic Circuits (DG, MK), pp. 577–582.
ICALP-1998-Grolmusz: A Degree-Decreasing Lemma for (MOD q — MOD p) Circuits (VG), pp. 215–222.
ICPR-1998-LagunovskyAK #image #recognition #reverse engineering: Recognition of integrated circuit images in reverse engineering (DL, SA, MK), pp. 1640–1642.
LICS-1998-JohannsenP #on the #proving: On Proofs about Threshold Circuits and Counting Hierarchies (JJ, CP), pp. 444–452.
DAC-1997-AlpertHK #clustering #multi: Multilevel Circuit Partitioning (CJA, JHH, ABK), pp. 530–533.
DAC-1997-CabodiCLQ #approach #clustering #effectiveness #scalability #traversal: Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits (GC, PC, LL, SQ), pp. 728–733.
DAC-1997-CongW #pipes and filters #synthesis: FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits (JC, CW), pp. 644–649.
DAC-1997-KrsticC #generative: Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits (AK, KTC), pp. 383–388.
DAC-1997-PantDC #energy #logic #network #optimisation #power management #random: Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks (PP, VD, AC), pp. 403–408.
DAC-1997-RainaBNMB #design #performance #testing: Efficient Testing of Clock Regenerator Circuits in Scan Designs (RR, RB, CN, RFM, CB), pp. 95–100.
DAC-1997-RoigCPP #automation #generative: Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits (OR, JC, MAP, EP), pp. 620–625.
DAC-1997-Roychowdhury #multi #performance #simulation: Efficient Methods for Simulating Highly Nonlinear Multi-Rate Circuits (JSR), pp. 269–274.
DAC-1997-SemenovYPPC #independence #synthesis: Synthesis of Speed-Independent Circuits from STG-Unfolding Segment (ALS, AY, EP, MAP, JC), pp. 16–21.
DAC-1997-WangVG #trade-off: An Investigation of Power Delay Trade-Offs on PowerPC Circuits (QW, SBKV, SG), pp. 425–428.
DAC-1997-YuanTK #estimation #statistics: Statistical Estimation of Average Power Dissipation in Sequential Circuits (LPY, CCT, SMK), pp. 377–382.
EDTC-1997-ChoiH #estimation: Improving the accuracy of support-set finding method for power estimation of combinational circuits (HC, SHH), pp. 526–530.
EDTC-1997-CornoPRR #sequence #testing: New static compaction techniques of test sequences for sequential circuits (FC, PP, MR, MSR), pp. 37–43.
EDTC-1997-CortadellaKKLY #composition #independence: Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis (JC, MK, AK, LL, AY), pp. 98–105.
EDTC-1997-DargelasGB #multi #named: MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits (AD, CG, YB), pp. 29–36.
EDTC-1997-DrechslerHSHB #testing: Testability of 2-level AND/EXOR circuits (RD, HH, HS, JH, BB), pp. 548–553.
EDTC-1997-Garcia-VargasGFR #algorithm #analysis #generative #scalability: An algorithm for numerical reference generation in symbolic analysis of large analog circuits (IGV, MG, FVF, ÁRV), pp. 395–399.
EDTC-1997-GavrilovGRBJV #performance: Fast power loss calculation for digital static CMOS circuits (SG, AG, SR, DB, LGJ, GV), pp. 411–415.
EDTC-1997-HsiaoRP #generative #testing #traversal #using: Sequential circuit test generation using dynamic state traversal (MSH, EMR, JHP), pp. 22–28.
EDTC-1997-IhsD #synthesis: Test synthesis for DC test of switched-capacitors circuits (HI, CD), p. 616.
EDTC-1997-IwamaHKS #benchmark #metric #random: Random benchmark circuits with controlled attributes (KI, KH, HK, SS), pp. 90–97.
EDTC-1997-ManichF #process: Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model (SM, JF), pp. 597–602.
EDTC-1997-SaxenaNH #approach #estimation #monte carlo: Monte-Carlo approach for power estimation in sequential circuits (VS, FNN, INH), pp. 416–420.
EDTC-1997-SchaumontVREB #multi #synthesis: Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications (PS, SV, LR, ME, IB), pp. 542–546.
EDTC-1997-StopjakovaM #monitoring #testing: CCII+ current conveyor based BIC monitor for IDDQ testing of complex CMOS circuits (VS, HARM), pp. 266–270.
EDTC-1997-TsengS #multi #standard #using: A gridless multi-layer router for standard cell circuits using CTM cells (HPT, CS), pp. 319–326.
EDTC-1997-WahbaB #fault: Connection error location and correction in combinational circuits (AMW, DB), pp. 235–241.
EDTC-1997-WalkerG97a #distributed #independence #simulation: Exploiting temporal independence in distributed preemptive circuit simulation (PW, SG), pp. 378–382.
STOC-1997-ImpagliazzoW #exponential: P = BPP if E Requires Exponential Circuits: Derandomizing the XOR Lemma (RI, AW), pp. 220–229.
STOC-1997-McCuaigRST: Permanents, Pfaffian Orientations, and Even Directed Circuits (Extended Abstract) (WM, NR, PDS, RT), pp. 402–405.
STOC-1997-PaturiSZ #bound #exponential: Exponential Lower Bounds for Depth 3 Boolean Circuits (RP, MES, FZ), pp. 86–91.
SAC-1997-CornoPRR #algorithm #generative #named: SAARA: a simulated annealing algorithm for test pattern generation for digital circuits (FC, PP, MR, MSR), pp. 228–232.
SAC-1997-MoonLK #2d #clustering #search-based: Genetic VLSI circuit partitioning with two-dimensional geographic crossover and zigzag mapping (BRM, YSL, CKK), pp. 274–278.
CAV-1997-PandeyB #evaluation #symmetry #verification: Exploiting Symmetry When Verifying Transitor-Level Circuits by Symbolic Trajectory Evaluation (MP, REB), pp. 244–255.
DAC-1996-BoglioloBR #estimation: Power Estimation of Cell-Based CMOS Circuits (AB, LB, BR), pp. 433–438.
DAC-1996-BorchersHB #behaviour #equation #generative: Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits (CB, LH, EB), pp. 236–239.
DAC-1996-Bryant #analysis: Bit-Level Analysis of an SRT Divider Circuit (REB), pp. 661–665.
DAC-1996-ChenPL #reduction: Desensitization for Power Reduction in Sequential Circuits (XC, PP, CLL), pp. 795–800.
DAC-1996-CortadellaKKLY #encoding #synthesis #tool support: Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis (JC, MK, AK, LL, AY), pp. 63–66.
DAC-1996-DesaiY #cpu #design #simulation #using #verification: A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation (MPD, YTY), pp. 125–130.
DAC-1996-DuttD #approach #clustering: A Probability-Based Approach to VLSI Circuit Partitioning (SD, WD), pp. 100–105.
DAC-1996-EliasM #modelling #scalability: Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency (PJHE, NPvdM), pp. 764–769.
DAC-1996-HuttonGRC #generative #random: Characterization and Parameterized Random Generation of Digital Circuits (MDH, JPG, JR, DGC), pp. 94–99.
DAC-1996-Johannes #clustering: Partitioning of VLSI Circuits and Systems (FMJ), pp. 83–87.
DAC-1996-KudvaGJ #distributed: A Technique for Synthesizing Distributed Burst-mode Circuits (PK, GG, HMJ), pp. 67–70.
DAC-1996-LimSPS #approach #estimation #process #statistics: A Statistical Approach to the Estimation of Delay Dependent Switching Activities in CMOS Combinational Circuits (YJL, KIS, HJP, MS), pp. 445–450.
DAC-1996-Matsunaga #equivalence #performance: An Efficient Equivalence Checker for Combinational Circuits (YM), pp. 629–634.
DAC-1996-PanL: Optimal Clock Period FPGA Technology Mapping for Sequential Circuits (PP, CLL), pp. 720–725.
DAC-1996-PomeranzR #on the #sequence #testing: On Static Compaction of Test Sequences for Synchronous Sequential Circuits (IP, SMR), pp. 215–220.
DAC-1996-RoychowdhuryM #scalability: Homotopy Techniques for Obtaining a DC Solution of Large-Scale MOS Circuits (JSR, RCM), pp. 286–291.
DAC-1996-SemenovY #petri net #using #verification: Verification of asynchronous circuits using Time Petri Net unfolding (ALS, AY), pp. 59–62.
DAC-1996-Sheehan #performance: An AWE Technique for Fast Printed Circuit Board Delays (BNS), pp. 539–543.
DAC-1996-TelicheveskyKW #analysis #performance: Efficient AC and Noise Analysis of Two-Tone RF Circuits (RT, KSK, JW), pp. 292–297.
DAC-1996-TutuianuDP #approximate: An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response (BT, FD, LTP), pp. 611–616.
DAC-1996-XiangVFP #design: Partial Scan Design Based on Circuit State Information (DX, SV, WKF, JHP), pp. 807–812.
TACAS-1996-Margaria #automation #detection #fault: Fully Automatic Verifcation and Error Detection for Parameterized Iterative Sequential Circuits (TMS), pp. 258–277.
STOC-1996-BartalFL #bound #graph #online #problem: Lower Bounds for On-line Graph Problems with Application to On-line Circuit and Optical Routing (YB, AF, SL), pp. 531–540.
STOC-1996-ChaudhuriR #complexity #strict: Deterministic Restrictions in Circuit Complexity (SC, JR), pp. 30–36.
STOC-1996-KushilevitzOR #linear #privacy: Characterizing Linear Size Circuits in Terms of Privacy (EK, RO, AR), pp. 541–550.
CAV-1996-Fujita #verification: Verification of Arithmetic Circuits by Comparing Two Similar Circuits (MF), pp. 159–168.
CAV-1996-KapurS #multi #product line #verification: Mechanically Verifying a Family of Multiplier Circuits (DK, MS), pp. 135–146.
CSL-1996-Otto #invariant #logic: The Logic of Explicitly Presentation-Invariant Circuits (MO), pp. 369–384.
DAC-1995-BryantC #diagrams #verification: Verification of Arithmetic Circuits with Binary Moment Diagrams (REB, YAC), pp. 535–541.
DAC-1995-ChouKW #3d #approach #simulation #using: Transient Simulations of Three-Dimensional Integrated Circuit Interconnect Using a Mixed Surface-Volume Approach (MC, TK, JW), pp. 485–490.
DAC-1995-DevadasM #bibliography #optimisation #power management: A Survey of Optimization Techniques Targeting Low Power VLSI Circuits (SD, SM), pp. 242–247.
DAC-1995-El-MalehMRM #on the #testing: On Test Set Preservation of Retimed Circuits (AHEM, TEM, JR, WM), pp. 176–182.
DAC-1995-JainBJ #abstraction #automation: Automatic Clock Abstraction from Sequential Circuits (SJ, REB, AJ), pp. 707–711.
DAC-1995-Kimura #verification: Residue BDD and Its Application to the Verification of Arithmetic Circuits (SK), pp. 542–545.
DAC-1995-KriegerBK #fault #multi #simulation: Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy (RK, BB, MK), pp. 339–344.
DAC-1995-LampaertGS: Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits (KL, GGEG, WMCS), pp. 445–449.
DAC-1995-LavagnoMSS #design #power management #synthesis: Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool (LL, PCM, AS, ALSV), pp. 254–260.
DAC-1995-LinJK #optimisation: Hierarchical Optimization of Asynchronous Circuits (BL, GGdJ, TK), pp. 712–717.
DAC-1995-MannePBHSMP: Computing the Maximum Power Cycles of a Sequential Circuit (SM, AP, RIB, GDH, FS, EM, MP), pp. 23–28.
DAC-1995-MehtaBOI #estimation #process: Accurate Estimation of Combinational Circuit Activity (HM, MB, RMO, MJI), pp. 618–622.
DAC-1995-MenezesPP #optimisation: Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization (NM, SP, LTP), pp. 690–695.
DAC-1995-Najm #correlation #estimation #feedback: Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits (FNN), pp. 612–617.
DAC-1995-NajmGH #estimation: Power Estimation in Sequential Circuits (FNN, SG, INH), pp. 635–640.
DAC-1995-NajmZ #process #worst-case: Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits (FNN, MYZ), pp. 623–627.
DAC-1995-NakamuraY #clustering #logic #matrix #optimisation #scalability: A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix (YN, TY), pp. 653–657.
DAC-1995-PomeranzR #logic #on the: On Synthesis-for-Testability of Combinational Logic Circuits (IP, SMR), pp. 126–132.
DAC-1995-RudnickP #generative #search-based #testing: Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation (EMR, JHP), pp. 183–188.
DAC-1995-SawasakiYL #implementation: Externally Hazard-Free Implementations of Asynchronous Circuits (MHS, CYC, BL), pp. 718–724.
DAC-1995-SinghalPRB: The Validity of Retiming Sequential Circuits (VS, CP, RLR, RKB), pp. 316–321.
DAC-1995-SwartzS #scalability #standard: Timing Driven Placement for Large Standard Cell Circuits (WS, CS), pp. 211–215.
DAC-1995-VanbekbergenWK #design #validation: A Design and Validation System for Asynchronous Circuits (PV, ARW, KK), pp. 725–730.
DAC-1995-VenkataramanHFRCP #agile #fault #simulation #using: Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists (SV, IH, WKF, EMR, SC, JHP), pp. 133–138.
DAC-1995-VinnakotaHS #design #difference: System-Level Design for Test of Fully Differential Analog Circuits (BV, RH, NJS), pp. 450–454.
FPLE-1995-ODonnell #architecture #education #functional #specification: From Transistors to Computer Architecture: Teaching Functional Circuit Specification in Hydra (JJO), pp. 195–214.
STOC-1995-BealsNT #complexity: More on the complexity of negation-limited circuits (RB, TN, KT), pp. 585–595.
STOC-1995-GoldmannH: Monotone circuits for connectivity have depth (log n)2-o(1) (Extended Abstract) (MG, JH), pp. 569–574.
ICALP-1995-KoblerW: New Collapse Consequences of NP Having Small Circuits (JK, OW), pp. 196–207.
ICML-1995-Lang95a #problem #search-based #synthesis: Hill Climbing Beats Genetic Search on a Boolean Circuit Synthesis Problem of Koza’s (KJL), pp. 340–343.
HPCA-1995-CappelloG #communication #network #performance #towards: Toward High Communication Performance through Compiled Communications on a Circuit Switched Interconnection Network (FC, CG), pp. 44–53.
CAV-1995-Bryant #multi #verification: Multipliers and Dividers: Insights on Arithmetic Circuits Verification (Extended Abstract) (REB), pp. 1–3.
CAV-1995-McMillan #using #verification: Trace Theoretic Verification of Asynchronous Circuits Using Unfoldings (KLM), pp. 180–195.
DAC-1994-ChenF #analysis #using: Transient Sensitivity Computation of MOSFET Circuits Using Iterated Timing Analysis and Selective-Tracing Waveform Eelaxation (CJC, WSF), pp. 581–585.
DAC-1994-ChouLCDL #clustering #logic: Circuit Partitioning for Huge Logic Emulation Systems (NCC, LTL, CKC, WJD, RL), pp. 244–249.
DAC-1994-DartuMQP #performance: A Gate-Delay Model for high-Speed CMOS Circuits (FD, NM, JQ, LTP), pp. 576–580.
DAC-1994-Kapoor #metric #process: Improving the Accuracy of Circuit Activity Measurement (BK), pp. 734–739.
DAC-1994-KondratyevKLVY #implementation #independence: Basic Gate Implementation of Speed-Independent Circuits (AK, MK, BL, PV, AY), pp. 56–62.
DAC-1994-MehrotraFL #approach #optimisation #probability: Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits (SM, PDF, WL), pp. 36–40.
DAC-1994-MonteiroDL #estimation #logic #performance #process: A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits (JCM, SD, BL), pp. 12–17.
DAC-1994-OchottaRC #agile #named #synthesis #tool support: ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits (ESO, RAR, LRC), pp. 24–30.
DAC-1994-ParulkarBN #representation: Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST (IP, MAB, CN), pp. 345–356.
DAC-1994-PomeranzR #combinator #fault #scalability #using: Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points (IP, SMR), pp. 358–364.
DAC-1994-PomeranzR94a #fault #on the: On Improving Fault Diagnosis for Synchronous Sequential Circuits (IP, SMR), pp. 504–509.
DAC-1994-PuriG #approach #clustering #composition #synthesis: A Modular Partitioning Approach for Asynchronous Circuit Synthesis (RP, JG), pp. 63–69.
DAC-1994-RiessDJ #clustering #scalability #using: Partitioning Very Large Circuits Using Analytical Placement Techniques (BMR, KD, FMJ), pp. 646–651.
DAC-1994-RudnickPGN #algorithm #framework #generative #search-based #testing: Sequential Circuit Test Generation in a Genetic Algorithm Framework (EMR, JHP, GSG, TMN), pp. 698–704.
DAC-1994-ShyurCP #on the #pipes and filters #testing: On Testing Wave Pipelined Circuits (JCS, HPC, TMP), pp. 370–374.
DAC-1994-TomitaYSH #design #fault #logic #multi: Rectification of Multiple Logic Design Errors in Multiple Output Circuits (MT, TY, FS, KH), pp. 212–217.
DAC-1994-XakellisN #estimation #process #statistics: Statistical Estimation of the Switching Activity in Digital Circuits (MGX, FNN), pp. 728–733.
EDAC-1994-AbderrahmanKS #estimation: Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits (AA, BK, YS), p. 658.
EDAC-1994-BaharCHMS #analysis #using: Timing Analysis of Combinational Circuits using ADD’s (RIB, HC, GDH, EM, FS), pp. 625–629.
EDAC-1994-BeckerD #diagrams #functional #testing: Testability of Circuits Derived from Functional Decision Diagrams (BB, RD), p. 667.
EDAC-1994-BrashearMOPM #analysis #performance #predict #statistics #using: Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis (RBB, NM, CO, LTP, MRM), pp. 332–337.
EDAC-1994-BurgunDGPS #complexity #logic #multi #synthesis: Multilevel Logic Synthesis of Very High Complexity Circuits (LB, ND, AG, EP, CS), p. 669.
EDAC-1994-DongenR #array #design: Advanced Analog Circuit Design on a Digital Sea-of-Gates Array (RvD, VR), pp. 70–74.
EDAC-1994-FrosslK #simulation: A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation (JF, TK), pp. 343–348.
EDAC-1994-FummiSS #approach #fault #functional #generative #testing: A Functional Approach to Delay Faults Test Generation for Sequential Circuits (FF, DS, MS), pp. 51–57.
EDAC-1994-GaiMR #fault #named #performance: TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits (SG, PLM, MSR), pp. 46–50.
EDAC-1994-GhatrajuAM #fixpoint #synthesis: High-Level Synthesis of Digital Circuits by Finding Fixpoints (LG, MHAEB, CM), pp. 94–98.
EDAC-1994-IsernF #fault: Test of Bridging Faults in Scan-based Sequential Circuits (EI, JF), pp. 366–370.
EDAC-1994-KeM #synthesis: Synthesis of Delay-Verifiable Two-Level Circuits (WK, PRM), pp. 297–301.
EDAC-1994-LinKL #approach #synthesis: Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach (KJL, JWK, CSL), pp. 178–183.
EDAC-1994-MichaelsS #modelling #simulation: Variable Accuracy Device Modeling for Event-Driven Circuit Simulation (KWM, AJS), pp. 557–561.
EDAC-1994-Rodriguez-MontanesF #analysis #fault #testing: Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability (RRM, JF), pp. 356–360.
EDAC-1994-RudnickHSP #algorithm #generative #search-based #testing: Application of Simple Genetic Algorithms to Sequential Circuit Test Generation (EMR, JGH, DGS, JHP), pp. 40–45.
EDAC-1994-SchneiderKK #verification: Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path (KS, TK, RK), pp. 648–652.
EDAC-1994-Stroele #analysis: Signature Analysis for Sequential Circuits with Reset (APS), pp. 113–118.
EDAC-1994-WangD #approximate #linear #optimisation #performance #using: An Efficient Yield Optimization Method Using A Two Step Linear Approximation of Circuit Performance (ZW, SWD), pp. 567–571.
EDAC-1994-WangFF: An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits (JHW, JTF, WSF), pp. 562–566.
EDAC-1994-WuLCL #clustering #distributed #fault #simulation: Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning (WCW, CLL, JEC, WYL), p. 661.
STOC-1994-Grolmusz #trade-off: A weight-size trade-off for circuits with MOD m gates (VG), pp. 68–74.
STOC-1994-JakobyRS #complexity: Circuit complexity: from the worst case to the average case (AJ, RR, CS), pp. 58–67.
STOC-1994-KrauseP #on the #power of: On the computational power of depth 2 circuits with threshold and modulo gates (MK, PP), pp. 48–57.
CAV-1994-RokickiM #automation #verification: Automatic Verification of Timed Circuits (TR, CJM), pp. 468–480.
LICS-1994-BrownH #category theory #design: Categories, Allegories and Circuit Design (CB, GH), pp. 372–381.
DAC-1993-AgrawalAV #distributed #generative #testing: Sequential Circuit Test Generation on a Distributed System (PA, VDA, JV), pp. 107–111.
DAC-1993-CarlsonC #order #performance: Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering (BSC, CYRC), pp. 361–366.
DAC-1993-ChakrabortyAB #design #fault #testing: Design for Testability for Path Delay faults in Sequential Circuits (TJC, VDA, MLB), pp. 453–457.
DAC-1993-ChakradharDPR #optimisation #using: Sequential Circuit Delay optimization Using Global Path Delays (STC, SD, MP, SGR), pp. 483–489.
DAC-1993-ChakravartyG #algorithm #fault: An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits (SC, YG), pp. 520–524.
DAC-1993-ChessL #fault #simulation: Bridge Fault simulation strategies for CMOS integrated Circuits (BC, TL), pp. 458–462.
DAC-1993-ChickermaneRBP: Non-Scan Design-for-Testability Techniques for Sequential Circuits (VC, EMR, PB, JHP), pp. 236–241.
DAC-1993-ChungWH #design #fault #logic: Diagnosis and Correction of Logic Design Errors in Digital Circuits (PYC, YMW, INH), pp. 503–508.
DAC-1993-CongS #algorithm #bottom-up #clustering #design #parallel: A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design (JC, MS), pp. 755–760.
DAC-1993-DamianiYM #logic #optimisation: Optimization of Combinational Logic Circuits Based on Compatible Gates (MD, JCYY, GDM), pp. 631–636.
DAC-1993-DharchoudhuryK #variability #worst-case: Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits (AD, SMK), pp. 154–158.
DAC-1993-Duvall #design #statistics: Practical Statistical Design of Complex Integrated Circuit Products (SGD), pp. 561–565.
DAC-1993-HaqueC #analysis #design #distributed #reliability: Analysis and Reliable Design of ECL Circuits with Distributed RLC Interconnections (MH, SC), pp. 697–701.
DAC-1993-HeebPR #modelling #using: Frequency Domain Microwave Modeling Using Retarded Partial Element Equivalent Circuits (HH, SP, AER), pp. 702–706.
DAC-1993-HuangJHHW #algorithm #scheduling: A Tree-Based Scheduling Algorithm for Control-Dominated Circuits (SHH, YLJ, CTH, YCH, JFW), pp. 578–582.
DAC-1993-KajiharaPKR #effectiveness #fault #generative #logic #testing: Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits (SK, IP, KK, SMR), pp. 102–106.
DAC-1993-KriplaniNYH #correlation: Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits (HK, FNN, PY, INH), pp. 384–388.
DAC-1993-LamBS #modelling #using: Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions (WKCL, RKB, ALSV), pp. 128–134.
DAC-1993-MeyerC #fault #multi #performance #simulation: Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy (WM, RC), pp. 515–519.
DAC-1993-Nagaraj #optimisation #performance: A New Optimizer for Performance Optimization of Analog Integrated Circuits (NSN), pp. 148–153.
DAC-1993-NagiCA #fault #named: DRAFTS: Discretized Analog Circuit Fault Simulator (NN, AC, JAA), pp. 509–514.
DAC-1993-OhlrichEGS #algorithm #identification #morphism #named #performance #using: SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm (MO, CE, EG, LS), pp. 31–37.
DAC-1993-PomeranzRU #fault #generative #named #testing: NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits (IP, SMR, PU), pp. 439–445.
DAC-1993-VisweswariahW #incremental #simulation: Incremental Event-Driven Simulation of Digital FET Circuits (CV, JAW), pp. 737–741.
DAC-1993-WooK #clustering #implementation #multi #performance: An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation. (NSW, JK), pp. 202–207.
DAC-1993-YangLYD #performance #simulation: An Efficient Non-Quasi-Static Diode Model for Circuit Simulation (ATY, YL, JTY, RRD), pp. 720–725.
ICDAR-1993-ItoTFHU #analysis #evaluation: Pattern analysis and evaluation of printed circuit boards (MI, YT, IF, MH, TU), pp. 798–801.
STOC-1993-AllenderJ #commutative #reduction: Depth reduction for noncommutative arithmetic circuits (EA, JJ), pp. 515–522.
STOC-1993-AspnesAFPW #online #scheduling: On-line load balancing with applications to machine scheduling and virtual circuit routing (JA, YA, AF, SAP, OW), pp. 623–631.
STOC-1993-GoldmannK #simulation: Simulating threshold circuits by majority circuits (MG, MK), pp. 551–560.
STOC-1993-ImpagliazzoPS #trade-off: Size-depth trade-offs for threshold circuits (RI, RP, MES), pp. 541–550.
STOC-1993-KarchmerW #nondeterminism: Characterizing non-deterministic circuit size (MK, AW), pp. 532–540.
STOC-1993-PudlakR: Modified ranks of tensors and the size of circuits (PP, VR), pp. 523–531.
HCI-SHI-1993-TakeguchiTO #analysis #information management #representation #scalability: A Knowledge Representation for Large Scale Integrated Circuit Failure Analysis (YT, TT, SO), pp. 92–97.
SEKE-1993-BombanaBCFSZ #analysis #functional #testing: An Expert Solution to Functional Testability Analysis of VLSI Circuits (MB, GB, PC, FF, DS, GZ), pp. 263–265.
HPDC-1993-AgrawalAV #generative #network: Test Pattern Generation for Sequential Circuits on a Network of Workstations (PA, VDA, JV), pp. 114–120.
CAV-1993-GuptaF #induction #parametricity #representation #using: Parametric Circuit Representation Using Inductive Boolean Functions (AG, ALF), pp. 15–28.
DAC-1992-AbramoviciRM #approach #exclamation #testing: Freeze!: A New Approach for Testing Sequential Circuits (MA, KBR, DTM), pp. 22–25.
DAC-1992-BhattacharyaAA #fault #generative #testing #using: Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions (DB, PA, VDA), pp. 159–164.
DAC-1992-ChakrabortyAB #fault #generative #logic #modelling #random #testing: Delay Fault Models and Test Generation for Random Logic Sequential Circuits (TJC, VDA, MLB), pp. 165–172.
DAC-1992-ChenDC: Circuit Enhancement by Eliminating Long False Paths (HCC, DHCD, SWC), pp. 249–252.
DAC-1992-ChengCDL #optimisation #performance: The Role of Long and Short Paths in Circuit Performance Optimization (SWC, HCC, DHCD, AL), pp. 543–548.
DAC-1992-DamianiM #equation #logic #optimisation: Recurrence Equations and the Optimization of Synchronous Logic Circuits (MD, GDM), pp. 556–561.
DAC-1992-DevadasKMW #logic #verification: Certified Timing Verification and the Transition Delay of a Logic Circuit (SD, KK, SM, ARW), pp. 549–555.
DAC-1992-DharchoudhuryK #approach #design #optimisation #worst-case: An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits (AD, SMK), pp. 704–709.
DAC-1992-GhoshDKW #estimation #process: Estimation of Average Switching Activity in Combinational and Sequential Circuits (AG, SD, KK, JW), pp. 253–259.
DAC-1992-JohnsonR #feedback #parallel: Parallel Waveform Relaxation of Circuits with Global Feedback Loops (TAJ, AER), pp. 12–15.
DAC-1992-JuS #incremental #simulation #using: Incremental Circuit Simulation Using Waveform Relaxation (YCJ, RAS), pp. 8–11.
DAC-1992-KriplaniNH #estimation: Maximum Current Estimation in CMOS Circuits (HK, FNN, INH), pp. 2–7.
DAC-1992-LeeH #fault #named #parallel #performance: HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits (HKL, DSH), pp. 336–340.
DAC-1992-LeeNB #generative #named #testing: SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits (KJL, CN, MAB), pp. 26–29.
DAC-1992-LeeR #analysis #evaluation #linear #named #using: AWEsymbolic: Compiled Analysis of Linear(ized) Circuits using Asymptotic Waveform Evaluation (JYL, RAR), pp. 213–218.
DAC-1992-LeeR92a #concurrent #fault #on the #performance #simulation: On Efficient Concurrent Fault Simulation for Synchronous Sequential Circuits (DHL, SMR), pp. 327–331.
DAC-1992-LiLAS #implementation #on the #problem: On the Circuit Implementation Problem (WNL, AL, PA, SS), pp. 478–483.
DAC-1992-LingKW #3d #approach #bound #simulation: A Boundary-Element Approach to Transient simulation of Three-Dimensional Integrated Circuit Interconnect (DDL, SK, JW), pp. 93–98.
DAC-1992-LinLE: Analyzing Cycle Stealing on Synchronous Circuits with Level-Sensitive Latches (IL, JAL, KE), pp. 393–398.
DAC-1992-MajumdarS #fault #on the #random testing #testing: On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits (AM, SS), pp. 341–346.
DAC-1992-MaulikCR #approach #programming #synthesis: A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis (PCM, LRC, RAR), pp. 698–703.
DAC-1992-NatarajanSHS #performance: Over-the-Cell Channel Routing for High Performance Circuits (SN, NAS, NDH, MS), pp. 600–603.
DAC-1992-PomeranzR #testing: At-Speed Delay Testing of Synchronous Sequential Circuits (IP, SMR), pp. 177–181.
DAC-1992-SaldanhaBS92a #algorithm #revisited: Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited (AS, RKB, ALSV), pp. 245–248.
DAC-1992-ShenoySBS #equivalence #on the: On the Temporal Equivalence of Sequential Circuits (NVS, KJS, RKB, ALSV), pp. 405–409.
STOC-1992-PatersonZ #multi: Shallow Multiplication Circuits and Wise Financial Investments (MP, UZ), pp. 429–437.
ICALP-1992-Straubing #complexity #first-order #power of: Circuit Complexity and the Expressive Power of Generalized First-Order Formulas (HS), pp. 16–27.
CAV-1992-JainKG #scalability #towards #verification: Towards a Verification Technique for Large Synchronous Circuits (PJ, PK, GG), pp. 109–122.
CAV-1992-McMillan #explosion #problem #using #verification: Using Unfoldings to Avoid the State Explosion Problem in the Verification of Asynchronous Circuits (KLM), pp. 164–177.
DAC-1991-BarkatullahC: A Transmission Line Simulator for GaAs Integrated Circuits (JSB, SC), pp. 746–751.
DAC-1991-BeerelM #testing: Testability of Asynchronous Timed Control Circuits with Delay Assumptions (PAB, THYM), pp. 446–451.
DAC-1991-BurchCL #model checking #representation: Representing Circuits More Efficiently in Symbolic Model Checking (JRB, EMC, DEL), pp. 403–407.
DAC-1991-Chen #clustering #concurrent #graph #scheduling: Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit (CIHC), pp. 287–290.
DAC-1991-Cheng #on the: On Removing Redundancy in Sequential Circuits (KTC), pp. 164–169.
DAC-1991-DeguchiIY #analysis #fault #logic #probability: Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits (YD, NI, SY), pp. 650–655.
DAC-1991-HussG #testing: Optimal Ordering of Analog Integrated Circuit Tests to Minimize Test Time (SDH, RSG), pp. 494–499.
DAC-1991-Kitamura #algorithm #fault #simulation: Sequential Circuit Fault Simulation by Fault Information Tracing Algorithm: FIT (YK), pp. 151–154.
DAC-1991-LavagnoKS #algorithm #synthesis: Algorithms for Synthesis of Hazard-Free Asynchronous Circuits (LL, KK, ALSV), pp. 302–308.
DAC-1991-LinL #automation #synthesis: Automatic Synthesis of Asynchronous Circuits (KJL, CSL), pp. 296–301.
DAC-1991-MattesWBD: Propagation Delay Calculation for Interconnection Nets on Printed Circuit Boards by Reflected Waves (HM, WW, GB, RD), pp. 567–572.
DAC-1991-Najm #probability #process: Transition Density, A Stochastic Measure of Activity in Digital Circuits (FNN), pp. 644–649.
DAC-1991-PaterasR #correlation #generative #multi #random #testing: Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits (SP, JR), pp. 347–352.
DAC-1991-PatilBP #generative #parallel #testing: Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors (SP, PB, JHP), pp. 155–159.
DAC-1991-RatzlaffGP #agile #named: RICE: Rapid Interconnect Circuit Evaluator (CLR, NG, LTP), pp. 555–560.
DAC-1991-SastryM #analysis #branch #process: A Branching Process Model for Observability Analysis of Combinational Circuits (SS, AM), pp. 452–457.
DAC-1991-SteinNGR #adaptation #named #simulation: ADAPTS: A Digital Transient Simulation Strategy for Integrated Circuits (ADS, TVN, BJG, RAR), pp. 26–31.
DAC-1991-TsayK #approach #optimisation #performance: An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement (RST, JK), pp. 620–625.
DAC-1991-WuR #effectiveness #evaluation: Delay Test Effectiveness Evaluation of LSSD-Based VLSI Vogic Circuits (DMW, CER), pp. 291–295.
DAC-1991-YangCYDH #modelling #parametricity #simulation: Modeling and Simulation of High-Frequency Integrated Circuits Based on Scattering Parameters (ATY, CHC, JTY, RRD, JPH), pp. 752–757.
DAC-1991-YoshikawaITSNK #optimisation: Timing Optimization on Mapped Circuits (KY, HI, HT, SS, NN, AK), pp. 112–117.
CAV-1991-Goldschlag #liveness #safety #verification: Mechanically Verifying Safety and Liveness Properties of Delay Insensitive Circuits (DMG), pp. 354–364.
ISLP-1991-FilkornSTW #case study #design #experience #industrial #scalability: Experiences from a Large Industrial Circuit Design Application (TF, RS, ET, PW), pp. 581–595.
DAC-1990-AdamiakAPRW #simulation: System Simulation of Printed Circuit Boards Including Packages and Connectors (KA, RA, JP, CR, AW), pp. 413–418.
DAC-1990-BurchCMD #model checking #using #verification: Sequential Circuit Verification Using Symbolic Model Checking (JRB, EMC, KLM, DLD), pp. 46–51.
DAC-1990-CaiNSM #assembly #layout #performance: A Data Path Layout Assembler for High Performance DSP Circuits (HC, SN, PS, HDM), pp. 306–311.
DAC-1990-Chakravarty #identification #on the: On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract) (SC), pp. 736–739.
DAC-1990-ChatterjeeH #approach #clustering: A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing (AC, RIH), pp. 36–39.
DAC-1990-ChoudhuryS #constraints #generative: Constraint Generation for Routing Analog Circuits (UC, ALSV), pp. 561–566.
DAC-1990-DevadasK #logic #optimisation #robust #synthesis: Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits (SD, KK), pp. 221–227.
DAC-1990-DeyBK #clustering: Corolla Based Circuit Partitioning and Resynthesis (SD, FB, GK), pp. 607–612.
DAC-1990-GhoshDN #verification: Verification of Interacting Sequential Circuits (AG, SD, ARN), pp. 213–219.
DAC-1990-HungWGS #parallel #simulation #using: Parallel Circuit Simulation Using Hierarchical Relaxation (GGH, YCW, KG, RAS), pp. 394–399.
DAC-1990-Ito #automation #testing: Automatic Incorporation of On-Chip Testability Circuits (NI), pp. 529–534.
DAC-1990-KuoLW #analysis #fault: A Fault Analysis Method for Synchronous Sequential Circuits (TYK, JYL, JFW), pp. 732–735.
DAC-1990-LeeH #automation #fault #generative #named #performance: SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits (HKL, DSH), pp. 660–666.
DAC-1990-NiermannCP #fault #memory management #named #performance #proving: Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator (TMN, WTC, JHP), pp. 535–540.
DAC-1990-ParkM #generative #logic #performance #testing: An Efficient Delay Test Generation System for Combinational Logic Circuits (ESP, MRM), pp. 522–528.
DAC-1990-SakallahMO #analysis #design: Analysis and Design of Latch-Controlled Synchronous Digital Circuits (KAS, TNM, KO), pp. 111–117.
DAC-1990-Tonkin #message passing #multi: Circuit Extraction on a Message-Based Multiprocessor (BAT), pp. 260–265.
DAC-1990-Yang #named #parallel: PARASPICE: A Parallel Circuit Simulator for Shared-Memory Multiprocessors (GCY), pp. 400–405.
STOC-1990-RazW #linear: Monotone Circuits for Matching Require Linear Depth (RR, AW), pp. 287–292.
STOC-1990-Szegedy #bound #communication #complexity #symmetry: Functions with Bounded Symmetric Communication Complexity and Circuits with mod m Gates (MS), pp. 278–286.
CAV-1990-BryantS #modelling #using #verification: Formal Verification of Digital Circuits Using Symbolic Ternary System Models (REB, CJHS), pp. 33–43.
CAV-1990-CamuratiGPR #model checking: The Use of Model Checking in ATPG for Sequential Circuits (PC, MG, PP, MSR), pp. 86–95.
CAV-1990-JosephsU #algebra: An Algebra for Delay-Insensitive Circuits (MBJ, JTU), pp. 343–352.
DAC-1989-BolsensRCM #analysis #behaviour #debugging #logic: Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour (IB, WDR, LJMC, HDM), pp. 513–518.
DAC-1989-ChoB #fault #generative #simulation: Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation (KC, REB), pp. 418–423.
DAC-1989-IshiuraTY #behaviour #logic #simulation #verification: Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits (NI, MT, SY), pp. 497–502.
DAC-1989-JonePP #concurrent #testing: A Scheme for Overlaying Concurrent Testing of VLSI Circuits (WBJ, CAP, MP), pp. 531–536.
DAC-1989-LeeHK #fault #generative #testing #using: Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits (HKL, DSH, KK), pp. 345–350.
DAC-1989-LueM: Extracting Schematic-like Information from CMOS Circuit Net-lists (WJL, LPM), pp. 690–693.
DAC-1989-NgV #framework #multi #scheduling #simulation: A Framework for Scheduling Multi-Rate Circuit Simulation (APCN, VV), pp. 19–24.
DAC-1989-OdentCM #feedback #implementation #multi #scalability: Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator (PO, LJMC, HDM), pp. 25–30.
DAC-1989-OgiharaMYM #effectiveness #generative #named #reliability #testing: MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits (TO, KM, GY, SM), pp. 519–524.
DAC-1989-SadayappanV #matrix #performance #simulation: Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers (PS, VV), pp. 13–18.
DAC-1989-Tamura #fault #functional #logic: Locating Functional Errors in Logic Circuits (KAT), pp. 185–191.
DAC-1989-WangKL #approach #fault #logic #robust #set: A New Approach to Derive Robust Sets for Stuck-open Faults in CMOS Combinational Logic Circuits (JFW, TYK, JYL), pp. 726–729.
DAC-1989-YangK #development #named #novel #simulation: iSMILE: A Novel Circuit Simulation Program with Emphasis on New Device Model Development (ATY, SMK), pp. 630–633.
DAC-1989-YihM #clustering #design #network: A Neural Network Design for Circuit Partitioning (JSY, PM), pp. 406–411.
DAC-1989-YuZYL #algorithm #behaviour #convergence #novel: A Novel Algorithm for Improving Convergence Behavior of Circuit Simulators (ZY, WZ, ZY, YEL), pp. 626–629.
STOC-1989-ReifT #integer: Optimal Size Integer Division Circuits (JHR, SRT), pp. 264–273.
STOC-1989-Yao: Circuits and Local Computation (ACCY), pp. 186–196.
ICALP-1989-McKenzieT #automaton #complexity: Automata Theory Meets Circuit Complexity (PM, DT), pp. 589–602.
DAC-1988-AgrawalCA #concurrent #contest #generative #named: Contest: A Concurrent Test Generator for Sequential Circuits (VDA, KTC, PA), pp. 84–89.
DAC-1988-BaerLMNSW #multi: A Notation for Describing Multiple Views of VLSI Circuits (JLB, MCL, LM, RN, LS, WW), pp. 102–107.
DAC-1988-BaltusA #generative #named #performance: SOLO: A Generator of Efficient Layouts from Optimized MOS Circuit Schematics (DGB, JA), pp. 445–452.
DAC-1988-BeattyB #analysis #incremental #performance #using: Fast Incremental Circuit Analysis Using Extracted Hierarchy (DLB, REB), pp. 495–500.
DAC-1988-BurchNYH #analysis #estimation #independence #reliability: Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits (RB, FNN, PY, DEH), pp. 294–299.
DAC-1988-Cai #multi: Multi-Pads, Single Layer Power Net Routing in VLSI Circuits (HC), pp. 183–188.
DAC-1988-ChangCS #performance: An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits (FCC, CFC, PS), pp. 282–287.
DAC-1988-Cheng #generative #testing: Split Circuit Model for Test Generation (WTC), pp. 96–101.
DAC-1988-Diss #compilation: Circuit Compilers don’t have to be Slow (WCD), pp. 622–627.
DAC-1988-HenkelG #layout #named #set #verification: RISCE — A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification (VH, UG), pp. 465–470.
DAC-1988-HillAHS #algorithm #fault #simulation: A New Two Task Algorithm for Clock Mode Fault Simulation in Sequential Circuits (FJH, EA, WKH, GQS), pp. 583–586.
DAC-1988-LiRS #logic #on the: On Path Selection in Combinational Logic Circuits (WNL, SMR, SS), pp. 142–147.
DAC-1988-MadreB #behaviour #comparison #correctness #proving #using: Proving Circuit Correctness Using Formal Comparison Between Expected and Extracted Behaviour (JCM, JPB), pp. 205–210.
DAC-1988-Meyer #data type: A Data Structure for Circuit Net Lists (SM), pp. 613–616.
DAC-1988-SaabYH #modelling: Delay Modeling and Time of Bipolar Digital Circuits (DGS, ATY, INH), pp. 288–293.
DAC-1988-Sechen #metaprogramming #using: Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing (CS), pp. 73–80.
DAC-1988-TakashimaIKTSS #comparison #functional #morphism #rule-based: A Circuit Comparison System with Rule-Based Functional Isomorphism Checking (MT, AI, SK, TT, TS, JiS), pp. 512–516.
DAC-1988-WeiRJ #behaviour #named #synthesis: BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping (RSW, SGR, JYJ), pp. 409–414.
STOC-1988-AggarwalCR #energy: Energy Consumption in VLSI Circuits (Preliminary Version) (AA, AKC, PR), pp. 205–216.
STOC-1988-KarchmerW: Monotone Circuits for Connectivity Require Super-logarithmic Depth (MK, AW), pp. 539–550.
ICALP-1988-RudichB #morphism #transitive: Optimal Circuits and Transitive Automorphism Groups (SR, LB), pp. 516–524.
PPEALS-1988-Rose #composition #implementation #parallel: The Parallel Decomposition and Implementation of an Integrated Circuit Global Router (JR), pp. 138–145.
LICS-1988-HoareG #correctness #logic: Partial Correctness of C-MOS Switching Circuits: An Exercise in Applied Logic (CARH, MJCG), pp. 28–36.
DAC-1987-ApteK #layout #standard: Strip Layout: A New Layout Methodology for Standard Circuit Modules (JA, GK), pp. 363–369.
DAC-1987-BryantBBCS #named: COSMOS: A Compiled Simulator for MOS Circuits (REB, DLB, KSB, KC, TJS), pp. 9–16.
DAC-1987-Cirit: Transistor Sizing in CMOS Circuits (MAC), pp. 121–124.
DAC-1987-Dion #performance: Fast Printed Circuit Board Routing (JD), pp. 727–734.
DAC-1987-HarjaniRC #framework #knowledge-based #prototype #synthesis: A Prototype Framework for Knowledge-Based Analog Circuit Synthesis (RH, RAR, LRC), pp. 42–49.
DAC-1987-LadjadjM #benchmark #metric: Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara Circuits (ML, JFM), pp. 509–515.
DAC-1987-LinN #named: KAHLUA: A Hierarchical Circuit Disassembler (BL, ARN), pp. 311–317.
DAC-1987-Rosenberg87a #interactive: A New Interactive Supply/Demand Router with Rip-Up Capability for Printed Circuit Boards (ER), pp. 721–726.
DAC-1987-Serlet #combinator #performance: Fast, Small, and Static Combinatorial CMOS Circuits (BS), pp. 451–458.
DAC-1987-Smith #hardware #scalability: A Hardware Switch Level Simulator for Large MOS Circuits (MTS), pp. 95–100.
DAC-1987-SuRT #named: HPEX: A Hierarchical Parasitic Circuit Extractor (SLS, VBR, TNT), pp. 566–569.
DAC-1987-TanTBVP #performance #self #simulation: A Fast Signature Simulation Tool for Built-In Self-Testing Circuits (SBT, KT, KB, PV, RP), pp. 17–25.
DAC-1987-VladimirescuWKBKDNJL #hardware #simulation: A Vector Hardware Accelerator with Circuit Simulation Emphasis (AV, DW, MK, ZB, AK, KD, KCN, NJ, SL), pp. 89–94.
DAC-1987-WebberS #simulation: Circuit Simulation on the Connection Machine (DMW, ALSV), pp. 108–113.
DAC-1987-Weise #functional #verification: Functional Verification of MOS Circuits (DW), pp. 265–270.
DAC-1987-WuWN #automation #design #representation #rule-based #verification: A Rule-Based Circuit Representation for Automated CMOS Design and Verification (CFEW, ASW, LMN), pp. 786–792.
DAC-1987-YuKL #adaptation #optimisation #testing #using: VLSI Circuit Testing Using an Adaptive Optimization Model (PSY, CMK, YHL), pp. 399–406.
STOC-1987-MillerT #complexity #parallel: Dynamic Parallel Complexity of Computational Circuits (GLM, SHT), pp. 254–263.
STOC-1987-Smolensky #algebra #bound #complexity #formal method: Algebraic Methods in the Theory of Lower Bounds for Boolean Circuit Complexity (RS), pp. 77–82.
DAC-1986-Beckett #c #modelling #network: MOS circuit models in Network C (WSB), pp. 171–178.
DAC-1986-ClarkeF #geometry #layout #named #recursion: Escher — a geometrical layout system for recursively defined circuits (EMC, YF), pp. 650–653.
DAC-1986-FreemanKLN #automation #layout #matrix #modelling: Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning (RDF, SMK, CGLH, MLN), pp. 418–424.
DAC-1986-JacobNP #analysis #empirical #multi #performance: An empirical analysis of the performance of a multiprocessor-based circuit simulator (GKJ, ARN, DOP), pp. 588–593.
DAC-1986-KurdahiP #estimation #named: PLEST: a program for area estimation of VLSI integrated circuits (FJK, ACP), pp. 467–473.
DAC-1986-Marlett #effectiveness #generative #testing: An effective test generation system for sequential circuits (RM), pp. 250–256.
DAC-1986-OdrynaNC: A workstation-mixed model circuit simulator (PO, KN, CC), pp. 186–192.
DAC-1986-SaitoSYK #array #logic #rule-based #synthesis: A rule-based logic circuit synthesis system for CMOS gate arrays (TS, HS, MY, NK), pp. 594–600.
DAC-1986-Sasao #generative #multi #named #synthesis #using: MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators (TS), pp. 86–93.
DAC-1986-ShihA #generative #physics #testing: Transistor-level test generation for physical failures in CMOS circuits (HCS, JAA), pp. 243–249.
DAC-1986-SupowitF #verification: A new method for verifying sequential circuits (KJS, SJF), pp. 200–207.
DAC-1986-WatanabeMNH #generative #knowledge-based #logic: Knowledge-based optimal IIL generator from conventional logic circuit descriptions (TW, TM, TN, NH), pp. 608–614.
DAC-1986-WeiweiX #algorithm #fault #generative #robust #testing: Robust test generation algorithm for stuck-open fault in CMOS circuits (WM, XL), pp. 236–242.
DAC-1986-WunderlichR #fault #modelling #on the: On fault modeling for dynamic MOS circuits (HJW, WR), pp. 540–546.
STOC-1986-Hastad #bound: Almost Optimal Lower Bounds for Small Depth Circuits (JH), pp. 6–20.
STOC-1986-Siegel #aspect-oriented #data flow: Aspects of Information Flow in VLSI Circuits (Extended Abstract) (AS), pp. 448–459.
ICLP-1986-Gupta86 #generative #prolog: Test-pattern Generation for VLSI Circuits in a Prolog Environment (RG), pp. 528–535.
DAC-1985-ChowdhuryB: The construction of minimal area power and ground nets for VLSI circuits (SUC, MAB), pp. 794–797.
DAC-1985-FinchMBS: A method for gridless routing of printed circuit boards (ACF, KJM, GJB, GS), pp. 509–515.
DAC-1985-HennionSC #algorithm #generative: A new algorithm for third generation circuit simulators: the one-step relaxation method (BH, PS, DC), pp. 137–143.
DAC-1985-Joseph #approach: An expert systems approach to completing partially routed printed circuit boards (RLJ), pp. 523–528.
DAC-1985-KaoFL #algorithm #automation: Algorithms for automatic transistor sizing in CMOS digital circuits (WHK, NF, CHL), pp. 781–784.
DAC-1985-KrasniewskiA #estimation #self: Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications (AK, AA), pp. 808–811.
DAC-1985-Lewis #hardware #simulation: A hardware engine for analogue mode simulation of MOS digital circuits (DML), pp. 345–351.
DAC-1985-Matson #megamodelling: Macromodeling of digital MOS VLSI Circuits (MDM), pp. 141–151.
DAC-1985-NgJ #approach #generative #graph: Generation of layouts from MOS circuit schematics: a graph theoretic approach (TKN, SLJ), pp. 39–45.
DAC-1985-OgiharaSM #automation #generative #named #parametricity #testing: PATEGE: an automatic DC parametric test generation system for series gated ECL circuits (TO, SS, SM), pp. 212–218.
DAC-1985-ReddyRA #generative #testing: Transistor level test generation for MOS circuits (MKR, SMR, PA), pp. 825–828.
DAC-1985-SakataK #comparison #linear: A circuit comparison system for bipolar linear LSI (TS, AK), pp. 429–434.
DAC-1985-Schaefer: A transistor-level logic-with-timing simulator for MOS circuits (TJS), pp. 762–765.
DAC-1985-ScottO: Magic’s circuit extractor (WSS, JKO), pp. 286–292.
DAC-1985-Wong #verification: Hierarchical circuit verification (YW), pp. 695–701.
SIGMOD-1985-BlainDMQ #design #process: Managing the Printed Circuit Board Design Process (TB, MD, RM, EQ), pp. 447–456.
POPL-1985-AnantharamanCFM #compilation: Compiling Path Expressions into VLSI Circuits (TSA, EMC, MJF, BM), pp. 191–204.
DAC-1984-BellonV #functional: Taking into account asynchronous signals in functional test of complex circuits (CB, RV), pp. 490–496.
DAC-1984-DeutschN #implementation #multi #simulation: A multiprocessor implementation of relaxation-based electrical circuit simulation (JTD, ARN), pp. 350–357.
DAC-1984-DoshiSS #interactive #logic #multi: THEMIS logic simulator — a mix mode, multi-level, hierarchical, interactive digital circuit simulator (MHD, RBS, DMS), pp. 24–31.
DAC-1984-EvansBD #algorithm #design #named #synthesis: ADL: An algorithmic design language for integrated circuit synthesis (WHE, JCB, NHD), pp. 66–72.
DAC-1984-GeusRRW #analysis #named: IDA: Interconnect delay analysis for integrated circuits (AJdG, JBR, MR, GW), pp. 536–541.
DAC-1984-GlasserH #optimisation: Delay and power optimization in VLSI circuits (LAG, LH), pp. 529–535.
DAC-1984-HollaarNCL #database #design #relational: The structure and operation of a relational database system in a cell-oriented integrated circuit design system (LAH, BEN, TMC, RAL), pp. 117–125.
DAC-1984-JhonK #analysis #concurrent #data flow #design: Deadlock analysis in the design of data-flow circuits (CSJ, RMK), pp. 705–707.
DAC-1984-KaoMS #design #named: ARIES: A workstation based, schematic driven system for circuit design (WHK, MHME, MLS), pp. 301–307.
DAC-1984-KawamuraTH #functional #memory management #verification: Functional verification of memory circuits from mask artwork data (MK, HT, KH), pp. 228–234.
DAC-1984-Kelly #automation #design: The CRITTER system: Automated critiquing of digital circuit designs (VEK), pp. 419–425.
DAC-1984-KozminskiK #algorithm #graph: An algorithm for finding a rectangular dual of a planar graph for use in area planning for VLSI integrated circuits (KK, EK), pp. 655–656.
DAC-1984-MarW #performance #verification: Performance verification of circuits (JM, YPW), pp. 479–483.
DAC-1984-McCormick #design #named: EXCL: A circuit extractor for IC designs (SPM), pp. 616–623.
DAC-1984-Parks #design: IGES as an interchange format for integrated circuit design (CHP), pp. 273–274.
DAC-1984-ReddyAJ #detection #fault #logic: A gate level model for CMOS combinational logic circuits with application to fault detection (SMR, VDA, SKJ), pp. 504–509.
STOC-1984-Alt #comparison: Comparison of Arithmetic Functions with Respect to Boolean Circuit Depth (Extended Abstract) (HA), pp. 466–470.
STOC-1984-AwerbuchIS #parallel: Finding Euler Circuits in Logarithmic Parallel Time (BA, AI, YS), pp. 249–257.
STOC-1984-Boppana #bound: Threshold Functions and Bounded Depth Monotone Circuits (RBB), pp. 475–479.
ICALP-1984-Jung #complexity #matrix #on the #performance #probability #problem: On Probabilistic Tape Complexity and Fast Circuits for Matrix Inversion Problems (Extended Abstract) (HJ), pp. 281–291.
DAC-1983-Acken #fault #testing: Testing for bridging faults (shorts) in CMOS circuits (JMA), pp. 717–718.
DAC-1983-Barke #layout #verification: A layout verification system for analog bipolar integrated circuits (EB), pp. 353–359.
DAC-1983-BarzilaiHSTW #logic #simulation #using: Simulating pass transistor circuits using logic simulation machines (ZB, LMH, GMS, DTT, LSW), pp. 157–163.
DAC-1983-BastianEFHM #simulation #specification: Symbolic Parasitic Extractor for Circuit Simulation (SPECS) (JDB, ME, PJF, CEH, LPM), pp. 346–352.
DAC-1983-ChangA #consistency: Consistency checking for MOS/VLSI circuits (NSC, RA), pp. 732–733.
DAC-1983-CohoonS #heuristic #problem: Heuristics for the Circuit Realization Problem (JC, SS), pp. 560–566.
DAC-1983-FukunagaYSK #approach #graph #using: Placement of circuit modules using a graph space approach (KF, SY, HSS, TK), pp. 465–471.
DAC-1983-Gupta #named: ACE: A Circuit Extractor (AG), pp. 721–725.
DAC-1983-JainA #generative #testing #using: Test generation for MOS circuits using D-algorithm (SKJ, VDA), pp. 64–70.
DAC-1983-KirkCSBT #array: Placement of irregular circuit elements on non-uniform gate arrays (HK, PDC, JAS, JDB, GLT), pp. 637–643.
DAC-1983-LaPaughL #testing: Total stuct-at-fault testing by circuit transformation (ASL, RJL), pp. 713–716.
DAC-1983-LoNB #data type: A data structure for MOS circuits (CYL, HNN, AKB), pp. 619–624.
DAC-1983-McGarityS: Experiments with the SLIM Circuit Compactor (RM, DPS), pp. 740–746.
DAC-1983-OgiharaMTKF #bidirectional #design #generative #testing: Test generation for scan design circuits with tri-state modules and bidirectional terminals (TO, SM, YT, KK, HF), pp. 71–78.
DAC-1983-OkazakiMY #multi: A multiple media delay simulator for MOS LSI circuits (KO, TM, TY), pp. 279–285.
DAC-1983-Ramachandran: An improved switch-level simulator for MOS circuits (VR), pp. 293–299.
DAC-1983-Smith #independence #layout: Technology-independent circuit layout (RJSI), pp. 390–393.
DAC-1983-TarolliH: Hierarchical circuit extraction with detailed parasitic capacitance (GMT, WJH), pp. 337–345.
STOC-1983-AhoUY #on the: On Notions of Information Transfer in VLSI Circuits (AVA, JDU, MY), pp. 133–139.
STOC-1983-ChandraFL83a #bound: Unbounded Fan-in Circuits and Associative Functions (AKC, SF, RJL), pp. 52–60.
STOC-1983-Fich #bound #parallel: New Bounds for Parallel Prefix Circuits (FEF), pp. 100–109.
STOC-1983-Sipser #complexity #set: Borel Sets and Circuit Complexity (MS), pp. 61–69.
STOC-1983-Valiant #bound #exponential #strict: Exponential Lower Bounds for Restricted Monotone Circuits (LGV), pp. 110–117.
ICALP-1983-ChandraFL #bound #constant #problem: Lower Bounds for Constant Depth Circuits for Prefix Problems (AKC, SF, RJL), pp. 109–117.
DAC-1982-Agrawal #analysis: Synchronous path analysis in MOS circuit simulator (VDA), pp. 629–635.
DAC-1982-BassetS #design #testing #top-down: Top down design and testability of VLSI circuits (PB, GS), pp. 851–857.
DAC-1982-BoseKLNPW #fault: A fault simulator for MOS LSI circuits (AKB, PK, CYL, HNN, EPS, KWW), pp. 400–409.
DAC-1982-CiesielskiK: An analytical method for compacting routing area in integrated circuits (MJC, EK), pp. 30–37.
DAC-1982-Kaplan #strict #verification: A “non-restrictive” artwork verification program for printed circuit boards (DK), pp. 551–558.
DAC-1982-KellerNE #design: A symbolic design system for integrated circuits (KHK, ARN, SE), pp. 460–466.
DAC-1982-LelarasmeeS #named #scalability: Relax: A new circuit for large scale MOS integrated circuits (EL, ALSV), pp. 682–687.
DAC-1982-MudgeRLA #image #layout #validation: Cellular image processing techniques for VLSI circuit layout validation and routing (TNM, RAR, RML, DEA), pp. 537–543.
DAC-1982-ShiraishiIKN #design #named: ICAD/PCB: Integrated computer aided design system for printed circuit boards (HS, MI, SK, MN), pp. 727–732.
DAC-1982-SyedGB #on the: On routing for custom integrated circuits (ZAS, AEG, MAB), pp. 887–893.
DAC-1982-TakashimaMCY #source code #verification: Programs for verifying circuit connectivity of mos/lsi mask artwork (MT, TM, TC, KY), pp. 544–550.
STOC-1982-Kissin #energy: Measuring Energy Consumption in VLSI Circuits: a Foundation (GK), pp. 99–104.
ILPC-1982-Eshghi82 #fault #logic #metalanguage #programming: Application of Meta-language Programming to Fault Finding in Logic Circuits (KE), pp. 240–246.
DAC-1981-AblasserJ #layout #recognition #verification: Circuit recognition and verification based on layout information (IA, UJ), pp. 684–689.
DAC-1981-AranoffA: Routing of printed circuit boards (SA, YA), pp. 130–136.
DAC-1981-BellonSG #hardware: Hardware description levels and test for complex circuits (CB, GS, JMG), pp. 213–219.
DAC-1981-Glasser #behaviour: The analog behavior of digital integrated circuits (LAG), pp. 603–612.
DAC-1981-IshiiIIYK #automation #diagrams #editing #interactive #logic: Automatic input and interactive editing systems of logic circuit diagrams (MI, YI, MI, MY, SK), pp. 639–645.
DAC-1981-KhokhaniPFSH: Placement of variable size circuits on LSI masterslices (KHK, AMP, WF, JS, DH), pp. 426–434.
DAC-1981-NgGK #parametricity #verification: A timing verification system based on extracted MOS/VLSI circuit parameters (PN, WG, RK), pp. 288–292.
DAC-1981-Ruehli #analysis #bibliography #logic #modelling #scalability #simulation: Survey of analysis, simulation and modeling for large scale logic circuits (AER), pp. 124–129.
DAC-1981-Ward #verification: A total verification of printed circuit artwork (MAW), pp. 720–725.
SOSP-1981-LudererCHKM #distributed: A Distributed UNIX System Based on a Virtual Circuit Switch (GWRL, HC, JPH, PAK, WTM), pp. 160–168.
DAC-1980-ChaoHY #approach #consistency #layout: A hierarchical approach for layout versus circuit consistency check (SPC, YSH, LMY), p. 269.
DAC-1980-ChaoHY80a #approach #consistency #layout: A hierarchical approach for layout versus circuit consistency check (SPC, YSH, LMY), pp. 270–276.
DAC-1980-CoteP #algorithm #problem: The interchange algorithms for circuit placement problems (LCC, AMP), pp. 528–534.
DAC-1980-DyerLMS #design #simulation: The use of graphics processors for circuit design simulation at GTE AE Labs (JD, AL, EJM, WDS), pp. 446–450.
DAC-1980-LorenzettiS #implementation #multi: An implementation of a saturated zone multi-layer printed circuit board router (MJL, RJSI), pp. 255–262.
DAC-1980-NhamB #multi: A multiple delay simulator for MOS LSI circuits (HNN, AKB), pp. 610–617.
DAC-1979-AkinoSKN #simulation #verification: Circuit simulation and timing verification based on MOS/LSI mask information (TA, MS, YK, TN), pp. 88–94.
DAC-1979-BennettSC #design #editing #interactive: Dynamic design rule checking in an interactive printed circuit editor (TCB, KRS, WMvC), pp. 330–336.
DAC-1979-DysartK #automation #bound #branch: An application of branch and bound method to automatic printed circuit board routing (LD, MK), pp. 494–499.
DAC-1979-IshiiYIS #diagrams #logic: An experimental input system of hand-drawn logic circuit diagram for LSI CAD (MI, MY, MI, HS), pp. 114–120.
DAC-1979-LallierJ: A new circuit placement program for FET chips (KWL, RKJ), pp. 109–113.
DAC-1979-LoslebenT #analysis: Topological analysis for VLSI circuits (PL, KT), pp. 461–473.
DAC-1979-Pimont #algorithm: New algorithms for grid-less routing of high density printed circuit boards (SP), p. 485.
DAC-1978-FairbairnR #interactive #layout #named: ICARUS: An interactive integrated circuit layout program (DGF, JAR), pp. 188–192.
DAC-1978-Fraser #design: Circuit design aids on unix (AGF), p. 234.
DAC-1978-InfanteBMYC #design #interactive: An Interactive Graphics System for the design of integrated circuits (BI, DB, BM, SY, EC), pp. 182–187.
DAC-1978-Marlett #generative #named #testing: EBT: A comprehensive test generation technique for highly sequential circuits (RM), pp. 335–339.
DAC-1978-Mory-Rauch: Pin assignment on a printed circuit board (LMR), pp. 70–73.
DAC-1978-PreasG #automation #layout: Methods for hierarchical automatic layout of custom LSI circuit masks (BP, CWG), pp. 206–212.
DAC-1978-StevensCBH #design #implementation #interactive: Implementation of an interactive printed circuit design system (KRS, WMvC, TCB, JAH), pp. 74–81.
STOC-1978-Tompa #trade-off #using: Time-Space Tradeoffs for Computing Functions, Using Connectivity Properties of their Circuits (MT), pp. 196–204.
ICALP-1978-ItaiR #graph: Covering a Graph by Circuits (AI, MR), pp. 289–299.
DAC-1977-BobasV #automation #design: A design automation system for printed circuit board assemblies (AB, JV), pp. 341–350.
DAC-1977-JaffeY #automation #diagrams #using: Automating analog circuit diagrams using a list processing language (RCJ, JPY), pp. 391–395.
DAC-1977-KollerL #design #standard: The siemens-avesta-system for computer-aided design of MOS-standard cell circuits (KWK, UL), pp. 153–157.
DAC-1977-PedroG #algorithm #automation #design #named #set: DOCIL: An automatic system for printed circuit board (PCB) designing. A board description language and an algorithm to connect a set of points (TdP, RG), pp. 174–181.
DAC-1977-SchulerC #fault #performance #simulation: An efficient method of fault simulation for digital circuits modeled from boolean gates and memories (DMS, RKC), pp. 230–238.
DAC-1977-YamadaWSITF #automation #generative #scalability #testing: Automatic test generation for large digital circuits (AY, NW, HS, OI, KT, SF), pp. 78–83.
DAC-1977-YoshidaMNCON #layout #scalability: A layout checking system for large scale integrated circuits (KY, TM, YN, TC, KO, SN), pp. 322–330.
STOC-1977-AngluinV #algorithm #performance #probability: Fast Probabilistic Algorithms for Hamiltonian Circuits and Matchings (DA, LGV), pp. 30–41.
STOC-1977-Itai #graph: Finding a Minimum Circuit in a Graph (AI), pp. 1–10.
DAC-1976-Cleemput #aspect-oriented #layout #on the #problem: On the topological aspects of the circuit layout problem (WMvC), pp. 441–450.
DAC-1976-GibsonN #layout #named: SLIC — Symbolic Layout of Integrated Circuits (DG, SN), pp. 434–440.
DAC-1976-GoundanH #clustering #fault #logic: Partitioning logic circuits to maximize fault resolution (AG, JPH), pp. 271–277.
DAC-1976-HellerF #approach: An organizational approach to routing printed circuit boards (BDH, RSF), pp. 168–171.
DAC-1976-Lerman #design #using: Computer aided design of printed circuit boards using remote graphics and TSO (HNL), pp. 104–108.
DAC-1976-Marks #design #documentation #online: Use of an on-line, time-shared graphics system to design and document printed circuit boards (LM), pp. 91–103.
DAC-1976-PerskyDS #automation #design #named: LTX — a system for the directed automatic design of LSI circuits (GP, DND, DGS), pp. 399–407.
DAC-1976-PiscatelliT: A solution to closeness checking of non-orthogonal printed circuit board wiring (RNP, PT), pp. 172–178.
DAC-1976-PreasBG #analysis #automation: Automatic circuit analysis based on mask information (BP, WLB, CWG), pp. 309–317.
DAC-1976-Schweikert #2d #algorithm #layout: A 2-dimensional placement algorithm for the layout of electrical circuits (DGS), pp. 408–416.
DAC-1976-WilcoxR #fault #interactive #logic #named: F/LOGIC — An interactive fault and logic simulator for digital circuits (PSW, HR), pp. 68–73.
STOC-1976-Valiant: Universal Circuits (Preliminary Report) (LGV), pp. 196–203.
DAC-1975-Fike #design #detection #fault #predict #question: Predicting fault detectability in combinational circuits — a new design tool? (JLF), pp. 290–295.
DAC-1975-Losleben #design #performance: Computer aided LSI circuit design: A relationship between topology and performance (PL), pp. 102–104.
DAC-1975-SchmidtD #algorithm: An iterative algorithm for placement and assignment of integrated circuits (DCS, LED), pp. 361–368.
DAC-1975-Valle #layout #relational: Relational data handling techniques in integrated circuit mask layout procedures (GV), pp. 407–413.
DAC-1974-ArimaTAO #algorithm #generative #heuristic #testing: A new heuristic test generation algorithm for sequential circuits (TA, MT, GA, JO), pp. 169–176.
DAC-1974-CleemputL #formal method #graph #layout #problem: An improved graph-theoretic model for the circuit layout problem (WMvC, JGL), pp. 82–90.
DAC-1974-Kjelkerud #generative #performance #source code #testing: A system of computer programs for efficient test generation for combinational switching circuits (EK), pp. 166–168.
DAC-1974-Peterson #automation #design: Automated design and manufacture of printed circuit boards (DLP), pp. 119–126.
DAC-1974-RosenbergB #design #named: CRITIC — an integrated circuit design rule checking program (LMR, CB), pp. 14–18.
DAC-1974-Summers #design #documentation: A Computer Aided System (CAS) for the design, manufacture, test, and documentation of digital Printed Circuit Boards (RJS), pp. 273–278.
DAC-1973-KernighanSP #algorithm: An optimum channel-routing algorithm for polycell layouts of integrated circuits (BWK, DGS, GP), pp. 50–59.
DAC-1973-MuraT #automation #generative #interactive: An interactive system for semi-automatic artwork generation of printed circuit boards (AM, MT), p. 60.
DAC-1973-Rubin: Assigning wires to layers of a printed circuit board (FR), pp. 22–32.
DAC-1973-Ruehli #design #logic: Electrical considerations in the computer aided design of logic circuit interconnections (AER), pp. 262–266.
DAC-1973-Shenkman #diagrams #functional #generative #logic: Circuit diagram generation via functional logic (SMS), pp. 267–273.
DAC-1973-So #multi: Pin assignment of circuit cards and the routability of multilayer printed wiring backplanes (HCS), pp. 33–43.
DAC-1972-HightowerU #agile #testing: A method for rapid testing of beam crossover circuits (DWH, BAU), pp. 144–156.
DAC-1972-Koren #automation #design: Pin assignment in automated printed circuit board design (NLK), pp. 72–79.
DAC-1972-MahS72a: Topologic class routing for printed circuit boards (LM, LS), pp. 80–93.
DAC-1972-SchweikertK #clustering: A proper model for the partitioning of electrical circuits (DGS, BWK), pp. 57–62.
DAC-1971-Nagamine #automation #design #logic #source code: An automated method for designing logic circuit diagnostic programs (MN), pp. 236–241.
DAC-1971-VishnubhotlaC #analysis #approach: A path analysis approach to the diagnosis of combinational circuits (SRV, YHC), pp. 222–230.
DAC-1970-AshleyMS #automation #metric: An automated micro measurement system for integrated circuit masks (FRA, EBM, HJS), pp. 17–27.
DAC-1970-BottorffSV #approach #automation #fault #memory management #problem #testing: An automatic system approach to the problem of memory circuit testing & fault diagnosis (PSB, MES, FJV), pp. 95–99.
DAC-1970-CampagnaF #design: Computer aided design of high density printed circuit boards (RC, PRF), p. 335.
DAC-1970-Farlow #design: Machine aids to the design of ceramic substrates containing integrated circuit chips (CWF), pp. 274–285.
DAC-1970-Flomenhoft #design #logic #testing: A system of computer aids for designing logic circuit tests (MJF), pp. 128–131.
DAC-1970-Yeager #automation #specification: Automation of test specifications for N/C printed circuit boards (TBY), pp. 190–202.
DAC-1969-Radke #predict: A justification of, and an improvement on, a useful rule for predicting circuit-to-pin ratios (CER), pp. 257–267.
DAC-1968-Baum: Printed circuit artwork checker (JDB).
DAC-1968-Bernstein #analysis #graph #online: Electronic circuit analysis with on-line graphs via a time-sharing terminal (SB).
DAC-1968-GarrettV #analysis #worst-case: Circuit frequency response analysis program with worst-case capabilities (FRWC) (SJG, THV).
DAC-1968-KadisTVHG #layout #source code: Building block programs for the layout of printed circuit boards utilizing integrated circuit packs (DAPSYS V.2) (RWK, KLT, WJVJ, WLH, CEG).
DAC-1968-Marin #algorithm #logic #on the #strict #synthesis #using: On a general synthesis algorithm of logical circuits using a restricted inventory of integrated circuits (MAM).
DAC-1968-Martin #design #layout: Computer-aided circuit layout and design (LCM).
DAC-1968-Murray-LassoK #analysis #online #optimisation: On-line circuit analysis and optimization with commercially available time-shared computer systems (MAML, FJK).
DAC-1968-Silverberg #layout #named: CLIC — computer layout of integrated circuits (MS).
DAC-1968-Weinberg #problem: Microelectronics and printed circuits: Problems and their solutions (LW).
DAC-1967-CalvinCEM #analysis #design: Design and analysis of electronic circuits (ELC, LCC, JRE, RSM).
DAC-1967-FiskCW #design #simulation: Topographic simulation as an aid to printed circuit board design (CJF, DLC, LEW).
DAC-1967-Malakoff #analysis: Coupling graphics and circuit analysis techniques (JLM).
DAC-1967-Pritchard #analysis #bibliography #source code: A survey of transient circuit analysis programs (GKP).
DAC-1967-SpitalnyG #design #online: On-line operation of CADIC (Computer aided design of integrated circuits) (AS, MJG).
SHARE-1965-FiskI #automation #layout #quote: “ACCEL”: automated circuit card etching layout (CJF, DDI).
SHARE-1965-SpitalnyMH #design: Computer aided design of integrated circuits (AS, WSM, GH).
SHARE-1964-Lavering #automation #design: AUTO CARD automated printed circuit board design (FBL).