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Travelled to:
1 × USA
Collaborated with:
S.Nejati M.Adedjouma L.C.Briand J.Hellebaut Y.Clement
Talks about:
softwar (1) shortag (1) integr (1) minim (1) embed (1) time (1) risk (1) cpu (1)

Person: Julien Begey

DBLP DBLP: Begey:Julien

Contributed to:

ASE 20132013

Wrote 1 papers:

ASE-2013-NejatiABHBC #cpu #embedded #risk management
Minimizing CPU time shortage risks in integrated embedded software (SN, MA, LCB, JH, JB, YC), pp. 529–539.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.