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Travelled to:
1 × Germany
Collaborated with:
G.Krampl
Talks about:
virtual (1) model (1) devic (1) vhdl (1) test (1) use (1)

Person: Marco Rona

DBLP DBLP: Rona:Marco

Contributed to:

DATE 20012001

Wrote 1 papers:

DATE-2001-RonaK #modelling #using
Modelling SoC devices for virtual test using VHDL (MR, GK), pp. 770–771.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.