Proceedings of the Sixth Conference on Design, Automation and Test in Europe
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Wolfgang Nebel, Ahmed Jerraya
Proceedings of the Sixth Conference on Design, Automation and Test in Europe
DATE, 2001.

SYS
DBLP
Scholar
Full names Links ISxN
@proceedings{DATE-2001,
	acmid         = "367072",
	address       = "Munich, Germany",
	editor        = "Wolfgang Nebel and Ahmed Jerraya",
	isbn          = "0-7695-0993-2",
	publisher     = "{ACM}",
	title         = "{Proceedings of the Sixth Conference on Design, Automation and Test in Europe}",
	year          = 2001,
}

Contents (157 items)

DATE-2001-DasguptaCNKC #abstraction #component #linear
Abstraction of word-level linear arithmetic functions from bit-level component descriptions (PD, PPC, AN, SK, AC), pp. 4–8.
DATE-2001-CabodiCQ #process
Biasing symbolic search by means of dynamic activity profiles (GC, PC, SQ), pp. 9–15.
DATE-2001-CharestRAB #open source
A methodology for interfacing open source systemC with a third party software (LC, MR, EMA, GB), p. 16.
DATE-2001-EconomakosOPPP #behaviour #synthesis
Behavioral synthesis with systemC (GE, PO, IP, IP, GKP), pp. 21–25.
DATE-2001-SiegmundM #communication #design #interface #modelling #multi #named
SystemCSV — an extension of SystemC for mixed multi-level communication modeling and interface-based system design (RS, DM), pp. 26–33.
DATE-2001-ZorianPTTPDSMR #embedded #tutorial
Embedded tutorial: TRP: integrating embedded test and ATE (YZ, PP, JPT, ICT, CEP, OPD, JS, PM, WR), pp. 34–37.
DATE-2001-StaaB #design #embedded #roadmap #tutorial
Embedded tutorial: current trends in the design of automotive electronic systems (PvS, TB), pp. 38–39.
DATE-2001-MartinSZBM #component #design
Component selection and matching for IP-based design (GM, RS, TZ, LB, GDM), pp. 40–46.
DATE-2001-DemmelerG #communication #framework #integration #platform
A universal communication model for an automotive system integration platform (TD, PG), pp. 47–54.
DATE-2001-BaghdadiLZJ #architecture #design #multi #performance
An efficient architecture model for systematic design of application-specific multiprocessor SoC (AB, DL, NEZ, AAJ), pp. 55–63.
DATE-2001-RufHGKRM #semantics #simulation
The simulation semantics of systemC (JR, DWH, JG, TK, WR, WM), pp. 64–70.
DATE-2001-Zhu #abstraction #design #named
MetaRTL: raising the abstraction level of RTL design (JZ), pp. 71–76.
DATE-2001-SvarstadNJ #communication #design #embedded #specification
A model for describing communication between aggregate objects in the specification and design of embedded systems (KS, GN, AAJ), pp. 77–85.
DATE-2001-IrionKVW #clustering #logic #performance #synthesis
Circuit partitioning for efficient logic BIST synthesis (AI, GK, HPEV, HJW), pp. 86–91.
DATE-2001-PaschalisGKPZ #embedded #self
Deterministic software-based self-testing of embedded processor cores (AMP, DG, NK, MP, YZ), pp. 92–96.
DATE-2001-LiW #fault #memory management
Memory fault diagnosis by syndrome compression (JFL, CWW), pp. 97–101.
DATE-2001-BayraktarogluO
Diagnosis for scan-based BIST: reaching deep into the signatures (IB, AO), pp. 102–111.
DATE-2001-Axelsson #architecture #tool support
Methods and tools for systems engineering of automotive electronic architectures (JA), p. 112.
DATE-2001-HettichT #architecture #challenge
Vehicle electric/electronic architecture — one of the most important challenges for OEM’s (GH, TT), pp. 112–113.
DATE-2001-PandayCM #architecture #named
AIL: description of a global electronic architecture at the vehicle scale (AP, DC, SM), p. 112.
DATE-2001-GoldbergPB #equivalence #satisfiability #using
Using SAT for combinational equivalence checking (EIG, MRP, RKB), pp. 114–121.
DATE-2001-RedaS #diagrams #equivalence #satisfiability #using
Combinational equivalence checking using Boolean satisfiability and binary decision diagrams (SR, AS), pp. 122–126.
DATE-2001-NovikovG #learning #multi #performance
An efficient learning procedure for multiple implication checks (YN, EIG), pp. 127–135.
DATE-2001-GajskiVRGBPECJ #concurrent #specification
C/C++: progress or deadlock in system-level specification (DG, EV, WR, VG, DB, JP, SEE, PC, GGdJ), pp. 136–137.
DATE-2001-LarssonP #framework
An integrated system-on-chip test framework (EL, ZP), pp. 138–144.
DATE-2001-ChandraC #performance #testing #using
Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding (AC, KC), pp. 145–149.
DATE-2001-BenabdenbiMM #testing
Testing TAPed cores and wrapped cores with the same test access mechanism (MB, WM, MM), pp. 150–155.
DATE-2001-ChiusanoCPW #on the #set
On applying the set covering model to reseeding (SC, SDC, PP, HJW), pp. 156–161.
DATE-2001-StaaBHPMKH #data transformation #design
Data management: limiter or accelerator for electronic design creativity (PvS, RB, HH, BP, JM, WK, WH), pp. 162–163.
DATE-2001-VandersteenWRSDEB #estimation #multi #performance
Efficient bit-error-rate estimation of multicarrier transceivers (GV, PW, YR, JS, SD, ME, IB), pp. 164–168.
DATE-2001-VanasscheGS #exponential #performance #simulation #using
Efficient time-domain simulation of telecom frontends using a complex damped exponential signal model (PV, GGEG, WMCS), pp. 169–175.
DATE-2001-NguyenJ #communication #simulation
Simulation method to extract characteristics for digital wireless communication systems (LN, VJ), pp. 176–181.
DATE-2001-HsiehCP #analysis #simulation
Microprocessor power analysis by labeled simulation (CTH, LC, MP), pp. 182–189.
DATE-2001-IyerM #architecture #power management #scalability
Power aware microarchitecture resource scaling (AI, DM), pp. 190–196.
DATE-2001-BeniniCMMPS #scheduling
Extending lifetime of portable systems by battery scheduling (LB, GC, AM, EM, MP, RS), pp. 197–203.
DATE-2001-GianiSHA #performance
Efficient spectral techniques for sequential ATPG (AG, SS, MSH, VDA), pp. 204–208.
DATE-2001-CornoRSV #on the
On the test of microprocessor IP cores (FC, MSR, GS, MV), pp. 209–213.
DATE-2001-PomeranzR #order #sequence
Sequence reordering to improve the levels of compaction achievable by static compaction procedures (IP, SMR), pp. 214–218.
DATE-2001-BensoCNP #analysis #distributed #fault #injection #open source
SEU effect analysis in an open-source router via a distributed fault injection environment (AB, SDC, GDN, PP), pp. 219–225.
DATE-2001-LockCM #framework #platform #programmable #question
The programmable platform: does one size fit all? (AL, RC, HM), pp. 226–227.
DATE-2001-LaiW #representation #slicing
Slicing tree is a complete floorplan representation (ML, DFW), pp. 228–232.
DATE-2001-CheungWC #clustering #logic #using
Further improve circuit partitioning using GBAW logic perturbation techniques (CCC, YLW, DIC), pp. 233–239.
DATE-2001-SaitohAT #clustering #performance #scheduling
Clustering based fast clock scheduling for light clock-tree (MS, MA, AT), pp. 240–245.
DATE-2001-DielissenMBHSHW #power management
Power-efficient layered turbo decoder processor (JD, JLvM, MB, FH, SS, JH, AvdW), pp. 246–251.
DATE-2001-SamiSSZZ #embedded
Exploiting data forwarding to reduce the power budget of VLIW embedded processors (MS, DS, CS, VZ, RZ), pp. 252–257.
DATE-2001-WormLW #architecture #design #performance #power management
Design of low-power high-speed maximum a priori decoder architectures (AW, HL, NW), pp. 258–267.
DATE-2001-NeauMR #complexity #using
Low complexity FIR filters using factorization of perturbed coefficients (CN, KM, KR), pp. 268–272.
DATE-2001-AcquavivaBR #adaptation #algorithm #multi #power management #streaming
An adaptive algorithm for low-power streaming multimedia processing (AA, LB, BR), pp. 273–279.
DATE-2001-LiuP #design #estimation
A static power estimation methodolodgy for IP-based design (XL, MCP), pp. 280–289.
DATE-2001-FavalliM #detection #fault #optimisation
Optimization of error detecting codes for the detection of crosstalk originated errors (MF, CM), pp. 290–296.
DATE-2001-CheynetNVRRV #automation #evaluation #program transformation #safety
System safety through automatic high-level code transformations: an experimental evaluation (PC, BN, RV, MR, MSR, MV), pp. 297–301.
DATE-2001-WahlAMR #modelling #optimisation
From DFT to systems test — a model based cost optimization tool (MGW, APA, CM, MR), pp. 302–306.
DATE-2001-DrozdL #float #online #performance #testing
Efficient on-line testing method for a floating-point adder (AVD, MVL), pp. 307–313.
DATE-2001-SilvaSAGLSTSRNSW #design #network
Design methodology for PicoRadio networks (JLdSJ, JS, MJA, CG, SFL, RCS, TT, MS, JMR, BN, ALSV, PKW), pp. 314–325.
DATE-2001-BadarogluHGDMGEB #generative #multi #scalability #simulation
High-level simulation of substrate noise generation from large digital circuits with multiple supplies (MB, MvH, VG, SD, HDM, GGEG, ME, IB), pp. 326–330.
DATE-2001-WernerGWR
Crosstalk noise in future digital CMOS circuits (CW, RG, AW, UR), pp. 331–335.
DATE-2001-KralicekJG #analysis #modelling
Modeling electromagnetic emission of integrated circuits for system analysis (PK, WJ, HG), pp. 336–340.
DATE-2001-FioriM #analysis
Analysis of EME produced by a microcontroller operation (FF, FM), pp. 341–347.
DATE-2001-RioRMPR #design #top-down
Top-down design of a xDSL 14-bit 4MS/s sigma-delta modulator in digital CMOS technology (RdR, JLdlR, FM, MBPV, ÁRV), pp. 348–352.
DATE-2001-DessoukyKLG #case study #design #reuse
Analog design for reuse — case study: very low-voltage sigma-delta modulator (MD, AK, MML, AG), pp. 353–360.
DATE-2001-GerfersM #design #power management
A design strategy for low-voltage low-power continuous-time sigma-delta A/D converters (FG, YM), pp. 361–369.
DATE-2001-NaiduJ #power management
Minimizing stand-by leakage power in static CMOS circuits (SRN, ETAFJ), pp. 370–376.
DATE-2001-ChangHM #functional #optimisation #symmetry #using
In-place delay constrained power optimization using functional symmetries (CWJC, BH, MMS), pp. 377–382.
DATE-2001-JozwiakC #composition #functional #metric
High-quality sub-function construction in functional decomposition based on information relationship measures (LJ, AC), pp. 383–390.
DATE-2001-EspejoEMO #logic #optimisation #reasoning
Generalized reasoning scheme for redundancy addition and removal logic optimization (JAE, LE, ESM, EO), pp. 391–397.
DATE-2001-ZengKC #approach #named #satisfiability
LPSAT: a unified approach to RTL satisfiability (ZZ, PK, MJC), pp. 398–402.
DATE-2001-FerrandiFSFF #behaviour #functional #generative #modelling #testing
Functional test generation for behaviorally sequential models (FF, GF, DS, AF, FF), pp. 403–410.
DATE-2001-HajjarCMAB #behaviour #quality #statistics #using #verification
High quality behavioral verification using statistical stopping criteria (AH, TC, IM, AAA, MB), pp. 411–419.
DATE-2001-PaulinKB #architecture #embedded #network #requirements #tool support
Network processors: a perspective on market requirements, processor architectures and embedded S/W tools (PGP, FK, PB), pp. 420–429.
DATE-2001-BeattieP #performance
Efficient inductance extraction via windowing (MWB, LTP), pp. 430–436.
DATE-2001-XuM #difference #modelling #performance #using
Efficient and passive modeling of transmission lines by using differential quadrature method (QX, PM), pp. 437–444.
DATE-2001-YuK #algorithm #distributed #performance
Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements (QY, ESK), pp. 445–450.
DATE-2001-Chen #grid #on the #power management
On the impact of on-chip inductance on signal nets under the influence of power grid noise (TC), pp. 451–459.
DATE-2001-UbarJP #diagrams #simulation
Timing simulation of digital circuits with binary decision diagrams (RU, AJ, ZP), pp. 460–466.
DATE-2001-Ruiz-de-ClavijoJBAV #logic #named
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model (PRdC, JJC, MJB, AJA, MV), pp. 467–471.
DATE-2001-HeringLM #functional #logic #named #parallel
dibSIM: a parallel functional logic simulator allowing dynamic load balancing (KH, JL, JM), pp. 472–478.
DATE-2001-KuterB #architecture #clustering
Architecture driven partitioning (JK, EB), pp. 479–487.
DATE-2001-PiguetRO #power management
Low-power systems on chips (SOCs) (CP, MR, TJFO), p. 488.
DATE-2001-Al-ArsG #array #behaviour #embedded #memory management
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs (ZAA, AJvdG), pp. 496–503.
DATE-2001-PomeranzR01a #detection #effectiveness #fault #generative #testing
Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage (IP, SMR), pp. 504–508.
DATE-2001-HashizumeIYT #detection #fault
CMOS open defect detection by supply current test (MH, MI, HY, TT), p. 509.
DATE-2001-ZengABA #identification
Full chip false timing path identification: applications to the PowerPCTM microprocessors (JZ, MSA, JB, JAA), pp. 514–519.
DATE-2001-WambacqVPREYLD
CAD for RF circuits (PW, GV, JRP, JSR, WE, BY, DEL, AD), pp. 520–529.
DATE-2001-Bazargan-SabetI #modelling #tool support #verification
Modeling crosstalk noise for deep submicron verification tools (PBS, FI), pp. 530–534.
DATE-2001-GaoW #algorithm #graph #modelling
A graph based algorithm for optimal buffer insertion under accurate delay models (YG, DFW), pp. 535–539.
DATE-2001-SarkarK #constraints
Repeater block planning under simultaneous delay and transition time constraints (PS, CKK), pp. 540–545.
DATE-2001-MacchiaruloBM #generative #layout #on the fly
On-the-fly layout generation for PTL macrocells (LM, LB, EM), pp. 546–551.
DATE-2001-SerdarS #automation
Automatic datapath tile placement and routing (TS, CS), pp. 552–559.
DATE-2001-NamSR #approach #incremental #satisfiability
A boolean satisfiability-based incremental rerouting approach with application to FPGAs (GJN, KAS, RAR), pp. 560–565.
DATE-2001-VareaA #embedded #modelling #petri net #specification
Dual transitions petri net based modelling technique for embedded systems specification (MV, BMAH), pp. 566–571.
DATE-2001-MarculescuN #analysis #modelling #probability
Probabilistic application modeling for system-level perfromance analysis (RM, AN), pp. 572–579.
DATE-2001-GiustoMH #embedded #estimation #execution #reliability
Reliable estimation of execution time of embedded software (PG, GM, EAH), pp. 580–589.
DATE-2001-AzaisBBR #implementation #linear
Implementation of a linear histogram BIST for ADCs (FA, SB, YB, MR), pp. 590–595.
DATE-2001-CherubalC #generative #parametricity #testing
Test generation based diagnosis of device parameters for analog circuits (SC, AC), pp. 596–602.
DATE-2001-Burdiek #generative #programming #using
Generation of optimum test stimuli for nonlinear analog circuits using nonlinear — programming and time-domain sensitivities (BB), pp. 603–609.
DATE-2001-Wilson #challenge #design #hardware
Managing the SoC design challenge with “Soft” hardware (RW), pp. 610–611.
DATE-2001-Doboli #constraints #design #embedded #latency
Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints (AD), pp. 612–619.
DATE-2001-XieW #graph #hardware #scheduling
Allocation and scheduling of conditional task graph in hardware/software co-synthesis (YX, WW), pp. 620–625.
DATE-2001-Parameswaran #hardware #performance
Code placement in hardware/software co-synthesis to improve performance and reduce cost (SP), pp. 626–632.
DATE-2001-AkgulM #hardware
System-on-a-chip processor synchronization support in hardware (BSA, VJMI), pp. 633–641.
DATE-2001-Hartenstein #configuration management
A decade of reconfigurable computing: a visionary retrospective (RWH), pp. 642–649.
DATE-2001-OuaissV #configuration management #memory management #synthesis
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers (IO, RV), pp. 650–657.
DATE-2001-FeketeKT #constraints #precedence
Optimal FPGA module placement with temporal precedence constraints (SPF, EK, JT), pp. 658–667.
DATE-2001-PasseroneWL #generative #graph #scheduling
Generation of minimal size code for scheduling graphs (CP, YW, LL), pp. 668–673.
DATE-2001-HoffmannNPBM #development #generative #quality #tool support #using
Generating production quality software development tools using a machine description language (AH, AN, SP, GB, HM), pp. 674–678.
DATE-2001-GauthierYJ #automation #embedded #generative #operating system
Automatic generation and targeting of application specific operating systems and embedded systems software (LG, SY, AAJ), pp. 679–685.
DATE-2001-KulkarniGMCM #embedded #layout #multi
Cache conscious data layout organization for embedded multimedia applications (CK, CG, MM, FC, HDM), pp. 686–693.
DATE-2001-GielenSCMR #challenge #design
Design challenges and emerging EDA solutions in mixed-signal IC design (GGEG, BS, HC, PM, JR), pp. 694–695.
DATE-2001-TagoHINSY #cpu
CPU for PlayStation 2 (HT, KH, NI, MN, MS, YY), p. 696.
DATE-2001-Mandapati #implementation
Implementation of the ATI flipper chip (AM), pp. 697–698.
DATE-2001-Narita #game studies #multi
SH-4 RISC microprocessor for multimedia, game machine (SN), pp. 699–701.
DATE-2001-MinatoI #combinator #problem #scalability #streaming
Streaming BDD manipulation for large-scale combinatorial problems (SiM, SI), pp. 702–707.
DATE-2001-LiuWHL #diagrams
Binary decision diagram with minimum expected path length (YYL, KHW, TH, CLL), pp. 708–712.
DATE-2001-ThorntonD #diagrams #graph transformation #using
Spectral decision diagrams using graph transformations (MAT, RD), pp. 713–719.
DATE-2001-JerrayaM #design
Electronic system design methodology: Europe’s positioning (AAJ, GM), pp. 720–721.
DATE-2001-NayakHCB #analysis #automation #fault #hardware #matlab #precise #synthesis
Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs (AN, MH, ANC, PB), pp. 722–728.
DATE-2001-NogueraB #algorithm #architecture #clustering #configuration management
A HW/SW partitioning algorithm for dynamically reconfigurable architectures (JN, RMB), p. 729.
DATE-2001-HuangM #configuration management #design #network #using
Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks (ZH, SM), p. 735.
DATE-2001-RufHKR #multi
Simulation-guided property checking based on a multi-valued AR-automata (JR, DWH, TK, WR), pp. 742–748.
DATE-2001-JungYC #analysis #multi #performance
Performance improvement of multi-processor systems cosimulation based on SW analysis (JJ, SY, KC), pp. 749–753.
DATE-2001-NicolescuYJ #communication #design #refinement
Mixed-level cosimulation for fine gradual refinement of communication in SoC design (GN, SY, AAJ), pp. 754–759.
DATE-2001-HoffmanKM #framework #performance
A framework for fast hardware-software co-simulation (AH, TK, HM), pp. 760–765.
DATE-2001-MadridPAR #design #modelling #reuse
Analog/mixed-signal IP modeling for design reuse (NMM, EJP, AJA, AR), pp. 766–767.
DATE-2001-JingnanVH #embedded #library
A Skill-based library for retargetable embedded analog cores (XJ, JCV, NH), pp. 768–769.
DATE-2001-RonaK #modelling #using
Modelling SoC devices for virtual test using VHDL (MR, GK), pp. 770–771.
DATE-2001-Castro-LopezFDR
Retargeting of mixed-signal blocks for SoCs (RCL, FVF, MDR, ÁRV), pp. 772–775.
DATE-2001-YeungHMMZ #integration #question #standard #what
Standard bus vs. bus wrapper: what is the best solution for future SoC integration? (CY, AH, GM, JM, JZ), pp. 776–777.
DATE-2001-GrunDN #embedded #memory management #power management
Access pattern based local memory customization for low power embedded systems (PG, NDD, AN), pp. 778–784.
DATE-2001-Zhu01a #analysis #memory management #pointer
Static memory allocation by pointer analysis and coloring (JZ), pp. 785–790.
DATE-2001-ConstantinidesCL #heuristic #multi
Heuristic datapath allocation for multiple wordlength systems (GAC, PYKC, WL), pp. 791–797.
DATE-2001-TeicaRV #automation #design #on the #using #verification
On the verification of synthesized designs using automatically generated transformational witnesses (ET, RR, RV), p. 798.
DATE-2001-CasavantGLMWA #generative #graph #simulation
Property-specific witness graph generation for guided simulation (AEC, AG, SL, AM, KW, PA), p. 799.
DATE-2001-StuikysZDM #component
Two approaches for developing generic components in VHDL (VS, GZ, RD, GM), p. 800.
DATE-2001-CichonB #data type #network
Annotated data types for addressed token passing networks (GC, WB), p. 801.
DATE-2001-NicoliciA #3d #design #testing #trade-off
Testability trade-offs for BIST RTL data paths: the case for three dimensional design space (NN, BMAH), p. 802.
DATE-2001-LechnerRH #comprehension #requirements #towards
Towards a better understanding of failure modes and test requirements of ADCs (AL, AR, BH), p. 803.
DATE-2001-QuasemG #fault #simulation
Exact fault simulation for systems on Silicon that protects each core’s intellectual property (MSQ, SKG), p. 804.
DATE-2001-DorschW #embedded #logic #testing #using
Using mission logic for embedded testing (RD, HJW), p. 805.
DATE-2001-DoboliV #analysis #network #scalability
A regularity-based hierarchical symbolic analysis method for large-scale analog networks (AD, RV), p. 806.
DATE-2001-OlbrichRB #algorithm #analysis #classification
An improved hierarchical classification algorithm for structural analysis of integrated circuits (MO, AR, EB), p. 807.
DATE-2001-SchmidtJKTN #automation #memory management #modelling
Automatic nonlinear memory power modelling (ES, GJ, LK, FT, WN), p. 808.
DATE-2001-ShinKC #optimisation
An operation rearrangement technique for power optimization in VLIM instruction fetch (DS, JK, NC), p. 809.
DATE-2001-GarnicaLH #power management #pseudo
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits (OG, JL, RH), p. 810.
DATE-2001-RoussellePBMV #embedded #fault
A register-transfer-level fault simulator for permanent and transient faults in embedded processors (CR, MP, AB, TM, HTV), p. 811.
DATE-2001-BertoniBF #architecture #encryption #finite #multi #performance
Efficient finite field digital-serial multiplier architecture for cryptography applications (GB, LB, PF), p. 812.
DATE-2001-WongMYCMPCLV #concurrent #summary
Task concurrency management methodology summary (CW, PM, PY, FC, HDM, ASP, NC, RL, DV), p. 813.
DATE-2001-Fiori
Susceptibility of analog cells to substrate interference (FF), p. 814.
DATE-2001-StaverenV #order
Order determination for frequency compensation of negative-feedback systems (AvS, CJMV), p. 815.
DATE-2001-YildizSV #bias #float #integer #linear #programming
Minimizing the number of floating bias voltage sources with integer linear programming (EY, AvS, CJMV), p. 816.
DATE-2001-CappuccinoC #performance
CMOS sizing rule for high performance long interconnects (GC, GC), p. 817.
DATE-2001-KoranneG #analysis #automation #geometry #layout #on the
On automatic analysis of geometrically proximate nets in VSLI layout (SK, OPG), p. 818.
DATE-2001-LienigJA #approach #named
AnalogRouter: a new approach of current-driven routing for analog circuits (JL, GJ, TA), p. 819.
DATE-2001-MoyaML #design #operating system
A hardware-software operating system for heterogeneous designs (JMM, FM, JCL), p. 820.
DATE-2001-TerechkoPE #architecture #clustering #named
PRMDL: a machine description language for clustered VLIW architectures (AT, EJDP, JTJvE), p. 821.
DATE-2001-BekooijEWB #behaviour #functional
Functional units with conditional input/output behavior in VLIW processors (MB, LJME, AvdW, NGB), p. 822.
DATE-2001-ZolfyMN #adaptation #concurrent #fault #simulation
Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation (MZ, SM, ZN), p. 823.
DATE-2001-PintoMEJ #constraints #scheduling
Constraint satisfaction for storage files with Fifos or stacks during scheduling (CAAP, BM, KvE, JAGJ), p. 824.

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