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Travelled to:
1 × France
Collaborated with:
B.Chen M.Fujita
Talks about:
identif (1) symbol (1) design (1) model (1) check (1) real (1) chip (1) bug (1)

Person: Michihiro Yamazaki

DBLP DBLP: Yamazaki:Michihiro

Contributed to:

EDAC-ETC-EUROASIC 19941994

Wrote 1 papers:

EDAC-1994-ChenYF #debugging #design #identification #model checking
Bug Identification of a Real Chip Design by Symbolic Model Checking (BC, MY, MF), pp. 132–136.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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