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Travelled to:
1 × Germany
Collaborated with:
M.Bekooij L.J.M.Engels A.v.d.Werf
Talks about:
processor (1) function (1) behavior (1) output (1) condit (1) input (1) vliw (1) unit (1)

Person: Natalino G. Busá

DBLP DBLP: Bus=aacute=:Natalino_G=

Contributed to:

DATE 20012001

Wrote 1 papers:

DATE-2001-BekooijEWB #behaviour #functional
Functional units with conditional input/output behavior in VLIW processors (MB, LJME, AvdW, NGB), p. 822.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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