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Travelled to:
1 × USA
Collaborated with:
M.P.Desai D.H.Hall
Talks about:
microprocessor (1) suitabl (1) robust (1) verif (1) model (1) elmor (1) delay (1) time (1) full (1) cmos (1)

Person: Nevine Nassif

DBLP DBLP: Nassif:Nevine

Contributed to:

DAC 19981998

Wrote 1 papers:

DAC-1998-NassifDH #modelling #robust #verification
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor (NN, MPD, DHH), pp. 230–235.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.