BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Used together with:
time (75)
model (71)
test (65)
fault (64)
circuit (55)

Stem delay$ (all stems)

456 papers:

CASECASE-2015-KimCLJ #design #estimation #using
Design of pitch controller for wind turbines using time-delay estimation (JK, JC, JL, MJ), pp. 1131–1136.
CASECASE-2015-SrinivasanBSSR #automation #machine learning #modelling #network #using
Modelling time-varying delays in networked automation systems with heterogeneous networks using machine learning techniques (SS, FB, GS, BS, SR), pp. 362–368.
DACDAC-2015-BockHKS #algorithm #modelling
Local search algorithms for timing-driven placement under arbitrary delay models (AB, SH, NK, US), p. 6.
DACDAC-2015-XuLP #adaptation #modelling #physics #statistics #using
Adaptive characterization and emulation of delay-based physical unclonable functions using statistical models (TX, DL, MP), p. 6.
DATEDATE-2015-CasuG
Rate-based vs delay-based control for DVFS in NoC (MRC, PG), pp. 1096–1101.
DATEDATE-2015-GuanTW0 #analysis #realtime
Delay analysis of structural real-time workload (NG, YT, YW, WY), pp. 223–228.
DATEDATE-2015-HuangTTC #architecture
Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects (SYH, MTT, KHHT, WTC), pp. 924–927.
DATEDATE-2015-IbrahimHBAABM #3d
Tackling the bottleneck of delay tables in 3D ultrasound imaging (AI, PH, AB, FA, MA, LB, GDM), pp. 1683–1688.
DATEDATE-2015-LiDC #algorithm #clustering #power of
A scan partitioning algorithm for reducing capture power of delay-fault LBIST (NL, ED, GC), pp. 842–847.
DATEDATE-2015-NgoEBDGNRR #detection #hardware #metric
Hardware trojan detection by delay and electromagnetic measurements (XTN, IE, SB, JLD, SG, ZN, JBR, BR), pp. 782–787.
DATEDATE-2015-SchneiderHKWW #fault #simulation
GPU-accelerated small delay fault simulation (ES, SH, MAK, XW, HJW), pp. 1174–1179.
DATEDATE-2015-SeylerSGNT #analysis #formal method
Formal analysis of the startup delay of SOME/IP service discovery (JRS, TS, MG, NN, JT), pp. 49–54.
DATEDATE-2015-ZhangPJLF #fault #self
Temperature-aware software-based self-testing for delay faults (YZ, ZP, JJ, HL, MF), pp. 423–428.
CHICHI-2015-LaseckiRMB #sequence
The Effects of Sequence and Delay on Crowd Work (WSL, JMR, AM, JPB), pp. 1375–1378.
CHICHI-2015-PatilHSKL #feedback #privacy
Interrupt Now or Inform Later?: Comparing Immediate and Delayed Privacy Feedback (SP, RH, RS, AK, AJL), pp. 1415–1418.
SIGIRSIGIR-2015-CrescenziKA #information management
Time Pressure and System Delays in Information Search (AC, DK, LA), pp. 767–770.
QAPLQAPL-2015-AldiniB #automaton #markov #similarity
Expected-Delay-Summing Weak Bisimilarity for Markov Automata (AA, MB), pp. 1–15.
CAVCAV-2015-ZouFZM #automation #difference #equation #safety #verification
Automatic Verification of Stability and Safety for Delay Differential Equations (LZ, MF, NZ, PNM), pp. 338–355.
CSLCSL-2015-Klein0 #game studies #lookahead #what
What are Strategies in Delay Games? Borel Determinacy for Games with Lookahead (FK, MZ), pp. 519–533.
ASEASE-2014-MaezawaNWH #ajax #using #validation
Validating ajax applications using a delay-based mutation technique (YM, KN, HW, SH), pp. 491–502.
CASECASE-2014-LiCW #policy #robust
A robust (r, Q) policy for a simple VMI system with inventory inaccuracy and time-delay (ML, FTSC, ZW), pp. 652–657.
CASECASE-2014-LiuK #communication #nondeterminism #parametricity
Passivity-based teleoperation system for robots with parametric uncertainty and communication delay (YCL, MHK), pp. 271–276.
CASECASE-2014-LuXJ #markov #process
A Markov Decision Process model for elective inpatient admission with delay announcement (YL, XX, ZJ), pp. 552–557.
CASECASE-2014-XueL #finite
Input-output finite-time stability of time-delay systems and its application to active vibration control (WX, KL), pp. 878–882.
DACDAC-2014-ChuangLJ #hybrid #synthesis
Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits (CCC, YHL, JHRJ), p. 6.
DATEDATE-2014-ChenCT #performance #simulation
An activity-sensitive contention delay model for highly efficient deterministic full-system simulations (SYC, CHC, RST), pp. 1–6.
DATEDATE-2014-LeeA #architecture #hybrid #novel #power management #using
A novel low power 11-bit hybrid ADC using flash and delay line architectures (HCL, JAA), pp. 1–4.
DATEDATE-2014-LongLY #analysis #bound #evaluation #modelling #multi
Analysis and evaluation of per-flow delay bound for multiplexing models (YL, ZL, XY), pp. 1–4.
DATEDATE-2014-ParkKK #design #multi #synthesis
Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs (KP, GK, TK), pp. 1–4.
DATEDATE-2014-Pomeranz14a #fault
Substituting transition faults with path delay faults as a basic delay fault model (IP), pp. 1–6.
DATEDATE-2014-RiefertCSBRB #approach #automation #effectiveness #fault #functional #generative #testing
An effective approach to automatic functional processor test generation for small-delay faults (AR, LMC, MS, PB, MSR, BB), pp. 1–6.
DATEDATE-2014-VijaykumarV #analysis #canonical #statistics #using
Statistical static timing analysis using a skew-normal canonical delay model (MV, VV), pp. 1–6.
DATEDATE-2014-ZhaoL #bound
Empowering study of delay bound tightness with simulated annealing (XZ, ZL), pp. 1–6.
ICSMEICSME-2014-CostaAMKH #empirical #integration
An Empirical Study of Delays in the Integration of Addressed Issues (DAdC, SLA, SM, UK, AEH), pp. 281–290.
LATALATA-2014-AnselmoGM #finite
Picture Codes with Finite Deciphering Delay (MA, DG, MM), pp. 88–100.
CHICHI-2014-BidwellHD #interface
Measuring operator anticipatory inputs in response to time-delay for teleoperated human-robot interfaces (JB, AH, SD), pp. 1467–1470.
CHICHI-2014-GreisAHM
I can wait a minute: uncovering the optimal delay time for pre-moderated user-generated content on public displays (MG, FA, NH, NM), pp. 1435–1438.
CHICHI-2014-VinesDM
Pay or delay: the role of technology when managing a low income (JV, PD, AM), pp. 501–510.
CSCWCSCW-2014-HwangYHYLMKS #mobile #named
TalkBetter: family-driven mobile intervention care for children with language delay (IH, CY, CH, DY, YL, CM, JK, JS), pp. 1283–1296.
AdaEuropeAdaEurope-2014-JaouenBPR #protocol
PDP 4PS : Periodic-Delayed Protocol for Partitioned Systems (AJ, EB, LP, TR), pp. 149–165.
CAiSECAiSE-2014-SenderovichWGM #mining #predict #process #queue
Queue Mining — Predicting Delays in Service Processes (AS, MW, AG, AM), pp. 42–57.
KDDKDD-2014-Chapelle #feedback #modelling
Modeling delayed feedback in display advertising (OC), pp. 1097–1105.
SACSAC-2014-JangKCH #replication
Impacts of delayed replication on the key-value store (MJ, WK, YC, JH), pp. 1757–1758.
SACSAC-2014-KuoT #in the cloud #incremental #virtual machine
Delay-based incrementally mapping of virtual machines in cloud computing systems (CFK, HWT), pp. 1498–1503.
LCTESLCTES-2014-BallabrigaCR #analysis
Cache-related preemption delay analysis for FIFO caches (CB, LKC, AR), pp. 33–42.
CASECASE-2013-AravamudhanML #estimation
“Network-theoretic” queuing delay estimation in theme park attractions (ASA, AM, HCL), pp. 776–782.
CASECASE-2013-TranH13a #composition #predict
Plug-and-play predictive control of modular nonlinear systems with coupling delays (TT, QPH), pp. 699–704.
CASECASE-2013-WangC #multi #policy #robust
A robust production control policy for a multiple-stage production system with inventory inaccuracy and time-delay (ZW, FTSC), pp. 77–82.
DACDAC-2013-KimJK #algorithm #problem
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem (JK, DJ, TK), p. 6.
DATEDATE-2013-ChaG #approach #detection #effectiveness #metric
Trojan detection via delay measurements: a new approach to select paths and vectors to maximize effectiveness and minimize cost (BC, SKG), pp. 1265–1270.
DATEDATE-2013-ChenRSIFC #analysis #process
A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation (YYC, AR, AS, GI, GF, DC), pp. 1789–1794.
DATEDATE-2013-MuradoreQF #network #predict
Model predictive control over delay-based differentiated services control networks (RM, DQ, PF), pp. 1117–1122.
DATEDATE-2013-SarrazinENBG #concurrent #design #detection #fault #performance
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection (SS, SE, LAdBN, YB, VG), pp. 1077–1082.
DATEDATE-2013-WagnerW #analysis #performance #statistics
Efficient variation-aware statistical dynamic timing analysis for delay test applications (MW, HJW), pp. 276–281.
DATEDATE-2013-ZhangYH0 #testing
Capturing post-silicon variation by layout-aware path-delay testing (XZ, JY, YH, XL), pp. 288–291.
CSCWCSCW-2013-AlvesF #named
Radiator: context propagation based on delayed aggregation (PA, PF), pp. 249–260.
CAiSECAiSE-2013-PikaAFHW #process #profiling
Profiling Event Logs to Configure Risk Indicators for Process Delays (AP, WMPvdA, CJF, AHMtH, MTW), pp. 465–481.
ICMLICML-c3-2013-JoulaniGS #feedback #learning #online
Online Learning under Delayed Feedback (PJ, AG, CS), pp. 1453–1461.
CCCC-2013-BertschNS #lr #on the #parsing
On LR Parsing with Selective Delays (EB, MJN, SS), pp. 244–263.
SOSPSOSP-2013-RavindranathPMB #mobile #named
Timecard: controlling user-perceived delays in server-based mobile applications (LR, JP, RM, HB), pp. 85–100.
CASECASE-2012-JungBT
A simplified time-delayed disturbance observer for position control of robot manipulators (SJ, YGB, MT), pp. 555–560.
CASECASE-2012-Kim #analysis #fuzzy #robust
Robust stability analysis of T-S fuzzy systems with interval time-varying delays via a relaxation technique (SHK), pp. 829–832.
CASECASE-2012-YanG #estimation #physics
Time-delay estimation of ultrasonic echoes based on the physical model matching (XY, LG), pp. 469–473.
DACDAC-2012-HuangLTCSCK #3d #testing
Small delay testing for TSVs in 3-D ICs (SYH, YHL, KHT, WTC, SKS, YFC, DMK), pp. 1031–1036.
DACDAC-2012-MeirR #analysis #biology #named #network #performance #using
BLAST: efficient computation of nonlinear delay sensitivities in electronic and biological networks using barycentric Lagrange enabled transient adjoint analysis (AM, JSR), pp. 301–310.
DATEDATE-2012-JafariJL #analysis #scheduling #worst-case
Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling (FJ, AJ, ZL), pp. 538–541.
DATEDATE-2012-KondratyevLMW #synthesis #trade-off
Exploiting area/delay tradeoffs in high-level synthesis (AK, LL, MM, YW), pp. 1024–1029.
DATEDATE-2012-MarinhoNPP #analysis #float #scheduling
Preemption delay analysis for floating non-preemptive region scheduling (JM, VN, SMP, IP), pp. 497–502.
DLTDLT-2012-GiambrunoMNS #bidirectional #finite
A Generalization of Girod’s Bidirectional Decoding Method to Codes with a Finite Deciphering Delay (LG, SM, JN, CS), pp. 471–476.
SACSAC-2012-HuH #network
A density-aware routing scheme in delay tolerant networks (CLH, BJH), pp. 563–568.
CAVCAV-2012-GuetGHMS #markov #search-based
Delayed Continuous-Time Markov Chains for Genetic Regulatory Circuits (CCG, AG, TAH, MM, AS), pp. 294–309.
CASECASE-2011-PuiuM #communication #realtime
The time delay control of CAN messages for real-time communication (DP, FM), pp. 631–636.
DACDAC-2011-AarestadLPAA #process
Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect (JA, CL, JP, DA, KA), pp. 534–539.
DACDAC-2011-ChenO #fault #statistics
Diagnosing scan clock delay faults through statistical timing pruning (MC, AO), pp. 423–428.
DACDAC-2011-LeeJ #framework #modelling #named #process
CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations (CYL, NKJ), pp. 866–871.
DACDAC-2011-WhatmoughDBD #power management
Error-resilient low-power DSP via path-delay shaping (PNW, SD, DMB, ID), pp. 1008–1013.
DATEDATE-2011-AgyekumN #communication #hardware #robust
A delay-insensitive bus-invert code and hardware support for robust asynchronous global communication (MYA, SMN), pp. 1370–1375.
DATEDATE-2011-BarceloGBS #estimation #performance #scalability
An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation (SB, XG, SAB, JS), pp. 1602–1607.
DATEDATE-2011-ChenLH #3d #architecture #towards
Architectural exploration of 3D FPGAs towards a better balance between area and delay (CIC, BCL, JDH), pp. 587–590.
DATEDATE-2011-EggersglusD #fault #generative #optimisation #pseudo #testing #using
As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization (SE, RD), pp. 1291–1296.
DATEDATE-2011-HsuL #optimisation
Clock gating optimization with delay-matching (SJH, RBL), pp. 643–648.
DATEDATE-2011-OnizawaMH #communication #monitoring
Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring (NO, AM, TH), pp. 776–781.
HCIDUXU-v2-2011-FleuryPL #challenge #ubiquitous #usability
Evaluating Ubiquitous Media Usability Challenges: Content Transfer and Channel Switching Delays (AF, JSP, LBL), pp. 404–413.
HCIHIMI-v2-2011-MurataHS #feedback #video #visual notation
Visual Feedback to Reduce Influence of Delay on Video Chatting (KM, MH, YS), pp. 157–164.
ICEISICEIS-v2-2011-JiaWLW #higher-order #research
The Research on Stability of Supply Chain under High Order Delay (SJ, LW, CL, QW), pp. 361–367.
QAPLQAPL-2011-AmanC #petri net
Time Delays in Membrane Systems and Petri Nets (BA, GC), pp. 47–60.
POPLPOPL-2011-EmmiQR #bound #scheduling
Delay-bounded scheduling (ME, SQ, ZR), pp. 411–422.
LDTALDTA-2011-JimM #semantics
Delayed semantic actions in Yakker (TJ, YM), p. 8.
CASECASE-2010-HanSL #predict #random
Modified generalized predictive power control for wireless networked systems with random delays (CH, DS, ZL), pp. 509–514.
DATEDATE-2010-AlpaslanDKMHW #simulation
NIM- a noise index model to estimate delay discrepancies between silicon and simulation (EA, JD, BK, AKM, WMH, PvdW), pp. 1373–1376.
DATEDATE-2010-BauerSF #analysis #network #worst-case
Worst-case end-to-end delay analysis of an avionics AFDX network (HB, JLS, CF), pp. 1220–1224.
DATEDATE-2010-GanapathyCGR #estimation #modelling #multi #variability
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability (SG, RC, AG, AR), pp. 417–422.
DATEDATE-2010-PeiLL #generative #testing
An on-chip clock generation scheme for faster-than-at-speed delay testing (SP, HL, XL), pp. 1353–1356.
DATEDATE-2010-PellizzoniSCCT #analysis #manycore #memory management
Worst case delay analysis for memory interference in multicore systems (RP, AS, JJC, MC, LT), pp. 741–746.
DATEDATE-2010-PengYTC #fault #process
High-quality pattern selection for screening small-delay defects considering process variations and crosstalk (KP, MY, MT, KC), pp. 1426–1431.
DATEDATE-2010-ZengC #metric #using
Interconnect delay and slew metrics using the beta distribution (JKZ, CPC), pp. 1329–1332.
ICGTICGT-2010-OrejasL #constraints #graph transformation #theorem proving
Delaying Constraint Solving in Symbolic Graph Transformation (FO, LL), pp. 43–58.
ICPRICPR-2010-AhmadNSNN #distributed #estimation #network #on the
On Clock Offset Estimation in Wireless Sensor Networks with Weibull Distributed Network Delays (AA, AN, ES, HNN, MNN), pp. 2322–2325.
HPCAHPCA-2010-BiDG #energy
Delay-Hiding energy management mechanisms for DRAM (MB, RD, CG), pp. 1–10.
CASECASE-2009-RamakrishnanR #analysis #linear
Delay-dependent stability analysis of linear system with additive time-varying delays (KR, GR), pp. 122–126.
CASECASE-2009-RoyBCC
HIV model with intracellular delay — a mathematical study (PKR, NB, JC, BC), pp. 373–378.
DATEDATE-2009-TaoL #grid #power management
Decoupling capacitor planning with analytical delay model on RLC power grid (YT, SKL), pp. 839–844.
DATEDATE-2009-YilmazC #detection #fault
Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects (MY, KC), pp. 1488–1493.
FoSSaCSFoSSaCS-2009-NeuhausserSK #markov #nondeterminism #process
Delayed Nondeterminism in Continuous-Time Markov Decision Processes (MRN, MS, JPK), pp. 364–379.
LATALATA-2009-GauwinNT #bound #concurrent #query
Bounded Delay and Concurrency for Earliest Query Answering (OG, JN, ST), pp. 350–361.
HCIHCI-NIMT-2009-TongW #recognition #speech
Compensate the Speech Recognition Delays for Accurate Speech-Based Cursor Position Control (QT, ZW), pp. 752–760.
HCIHIMI-DIE-2009-ShinPC #bound #detection
Virtual Convex Polygon Based Hole Boundary Detection and Time Delay Based Hole Detour Scheme in WSNs (IS, NDP, HC), pp. 619–627.
CASECASE-2008-Morrison #evolution
Flow lines with regular service times: Evolution of delay, state dependent failures and semiconductor wafer fabrication (JRM), pp. 247–252.
DACDAC-2008-HeloueN #analysis #modelling
Parameterized timing analysis with general delay models and arbitrary variation sources (KRH, FNN), pp. 403–408.
DACDAC-2008-HomayounPMV #embedded #energy #performance #scalability
Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency (HH, SP, MAM, AVV), pp. 68–71.
DACDAC-2008-KellerTK #challenge #modelling
Challenges in gate level modeling for delay and SI at 65nm and below (IK, KHT, VK), pp. 468–473.
DACDAC-2008-WangLZTYTCN #scheduling
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays (YW, WSL, XZ, JT, CY, JT, WC, JN), pp. 223–226.
DATEDATE-2008-ClineCBTS #modelling
Transistor-Specific Delay Modeling for SSTA (BC, KC, DB, AT, SS), pp. 592–597.
DATEDATE-2008-KeezerMD #injection #multi
Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications (DCK, DM, PD), pp. 1486–1491.
DATEDATE-2008-NagpalGK #approach #design #using
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements (CN, RG, SPK), pp. 354–359.
DATEDATE-2008-PakbazniaP #using
Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting (EP, MP), pp. 385–390.
HPCAHPCA-2008-GuptaRSWB #commit #induction #named
DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors (MSG, KKR, MDS, GYW, DMB), pp. 381–392.
LCTESLCTES-2008-HomayounPMV #adaptation #embedded #energy #performance
Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors (HH, SP, MAM, AVV), pp. 71–78.
CASECASE-2007-KirkpatrickC
DC Machine Control with Time Delay and a PID Controller (KPK, GMC), pp. 783–787.
DACDAC-2007-AhmedTJ #design #fault #generative
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design (NA, MT, VJ), pp. 533–538.
DACDAC-2007-ChengCW07a #named #synthesis
DDBDD: Delay-Driven BDD Synthesis for FPGAs (LC, DC, MDFW), pp. 910–915.
DACDAC-2007-GandikotaCBSB #analysis #set
Top-k Aggressors Sets in Delay Noise Analysis (RG, KC, DB, DS, MRB), pp. 174–179.
DACDAC-2007-HuangCCN
Clock Period Minimization with Minimum Delay Insertion (SHH, CHC, CMC, YTN), pp. 970–975.
DACDAC-2007-LiuS #predict #process #scalability #statistics
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations (QL, SSS), pp. 497–502.
DACDAC-2007-RamanCOD #multi
Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution (BR, SC, WTO, SD), pp. 738–743.
DACDAC-2007-RoyMC #nondeterminism
Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew (AR, NHM, MHC), pp. 184–187.
DATEDATE-2007-BarajasCCMGCBI #behaviour #interactive #modelling #optimisation
Interactive presentation: Behavioral modeling of delay-locked loops and its application to jitter optimization in ultra wide-band impulse radio systems (EB, RC, DC, DM, JLG, IC, SB, MI), pp. 1430–1435.
DATEDATE-2007-FavalliM #detection #fault #interactive
Interactive presentation: Pulse propagation for the detection of small delay defects (MF, CM), pp. 1295–1300.
DATEDATE-2007-JuCR #analysis #scheduling
Accounting for cache-related preemption delay in dynamic priority schedulability analysis (LJ, SC, AR), pp. 1623–1628.
DATEDATE-2007-KurraSP #synthesis
The impact of loop unrolling on controller delay in high level synthesis (SK, NKS, PRP), pp. 391–396.
DATEDATE-2007-LinXZ #design #network
Design closure driven delay relaxation based on convex cost network flow (CL, AX, HZ), pp. 63–68.
DATEDATE-2007-NiM #self
Self-heating-aware optimal wire sizing under Elmore delay model (MN, SOM), pp. 1373–1378.
DATEDATE-2007-RosselloBBS #statistics #testing
Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs (JLR, CdB, SAB, JS), pp. 1271–1276.
DATEDATE-2007-SatishRK #approach #communication #constraints #graph #multi #optimisation #scheduling
A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessors (NS, KR, KK), pp. 57–62.
DATEDATE-2007-SilvaSP #performance
Efficient computation of the worst-delay corner (LGeS, LMS, JRP), pp. 1617–1622.
DATEDATE-2007-TadesseSLBG #analysis #modelling #satisfiability #using
Accurate timing analysis using SAT and pattern-dependent delay models (DT, DS, EL, RIB, JG), pp. 1018–1023.
DATEDATE-2007-WangY #fault #synthesis #testing
High-level test synthesis for delay fault testability (SJW, THY), pp. 45–50.
HCIHIMI-IIE-2007-MurataNSKT #feedback #visual notation
Visual Feedback to Reduce the Negative Effects of Message Transfer Delay on Voice Chatting (KM, MN, YS, IK, YT), pp. 95–101.
OOPSLAOOPSLA-2007-FahndrichX #invariant
Establishing object invariants with delayed types (MF, SX), pp. 337–350.
CSLCSL-2007-BaganDG #constant #on the #query
On Acyclic Conjunctive Queries and Constant Delay Enumeration (GB, AD, EG), pp. 208–222.
RTARTA-2007-Santo
Delayed Substitutions (JES), pp. 169–183.
CASECASE-2006-LeeLS #clustering #graph
Token delays and generalized workload balancing for timed event graphs with application to cluster tool operation (TEL, HYL, RSS), pp. 93–99.
DACDAC-2006-AhmedTJ #fault
Timing-based delay test for screening small delay defects (NA, MT, VJ), pp. 320–325.
DACDAC-2006-AksoyCFM #constraints #integer #linear #optimisation #programming #satisfiability #synthesis #using
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming (LA, EACdC, PFF, JM), pp. 669–674.
DACDAC-2006-FatemiNP #analysis #logic #statistics #using
Statistical logic cell delay analysis using a current-based model (HF, SN, MP), pp. 253–256.
DACDAC-2006-GuptaGP #agile #estimation #specification
Rapid estimation of control delay from high-level specifications (GRG, MG, PRP), pp. 455–458.
DACDAC-2006-LinCC #clustering #optimisation
Optimal simultaneous mapping and clustering for FPGA delay optimization (JYL, DC, JC), pp. 472–477.
DACDAC-2006-PengL #constraints #power management
Low-power repeater insertion with both delay and slew rate constraints (YP, XL), pp. 302–307.
DATEDATE-2006-GillPW #analysis #fault #logic
Soft delay error analysis in logic circuits (BSG, CAP, FGW), pp. 47–52.
DATEDATE-2006-NazarianP #analysis
Cell delay analysis based on rate-of-current change (SN, MP), pp. 539–544.
DATEDATE-2006-PolianF #constraints #functional #testing
Functional constraints vs. test compression in scan-based delay testing (IP, HF), pp. 1039–1044.
DATEDATE-2006-RosselloS #fault #identification
A compact model to identify delay faults due to crosstalk (JLR, JS), pp. 902–906.
DATEDATE-2006-YangC #fault
Timing-reasoning-based delay fault diagnosis (KY, KTC), pp. 418–423.
DATEDATE-DF-2006-CampobelloCCM #network
GALS networks on chip: a new solution for asynchronous delay-insensitive links (GC, MC, CC, DM), pp. 160–165.
DocEngDocEng-2006-Maitre #documentation #multi #xml
Describing multistructured XML documents by means of delay nodes (JLM), pp. 155–164.
VLDBVLDB-2006-CohenFKKS
Full Disjunctions: Polynomial-Delay Iterators in Action (SC, IF, YK, BK, YS), pp. 739–750.
VLDBVLDB-2006-NarayananDMR #query
Delay Aware Querying with Seaweed (DN, AD, RM, AITR), pp. 727–738.
CHICHI-2006-GergleKF #collaboration #feedback #performance #visual notation
The impact of delayed visual feedback on collaborative performance (DG, REK, SRF), pp. 1303–1312.
LCTESLCTES-2006-YanSG #architecture #configuration management #estimation #implementation
Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures (LY, TS, NG), pp. 182–188.
PPoPPPPoPP-2006-BrevikNW #bound #parallel #predict
Predicting bounds on queuing delay for batch-scheduled parallel machines (JB, DN, RW), pp. 110–118.
CSLCSL-2006-Bagan #linear #query
MSO Queries on Tree Decomposable Structures Are Computable with Linear Delay (GB), pp. 167–181.
DACDAC-2005-ChangZNV #analysis #parametricity #statistics
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions (HC, VZ, SN, CV), pp. 71–76.
DACDAC-2005-KajiharaFWMHS #process
Path delay test compaction with process variation tolerance (SK, MF, XW, TM, SH, YS), pp. 845–850.
DACDAC-2005-TennakoonS #modelling #performance
Efficient and accurate gate sizing with piecewise convex delay models (HT, CS), pp. 807–812.
DACDAC-2005-ZhanSLPNS #analysis #statistics
Correlation-aware statistical timing analysis with non-gaussian delay distributions (YZ, AJS, XL, LTP, DN, MS), pp. 77–82.
DACDAC-2005-ZykovMJVS #architecture #novel #performance #trade-off
High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs (AVZ, EM, MFJ, GdV, AS), pp. 270–273.
DATEDATE-2005-BeckBKPLP #design #generative #implementation #logic #quality
Logic Design for On-Chip Test Clock Generation — Implementation Details and Impact on Delay Test Quality (MB, OB, MK, FP, XL, RP), pp. 56–61.
DATEDATE-2005-BhuniaMRR #novel #testing
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application (SB, HMM, AR, KR), pp. 1136–1141.
DATEDATE-2005-BouesseRDG #formal method
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement (GFB, MR, SD, FG), pp. 424–429.
DATEDATE-2005-ChandrasekarH #fault #generative #incremental #integration #learning #performance #satisfiability #testing
Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation (KC, MSH), pp. 1002–1007.
DATEDATE-2005-DattaBMBR #design #modelling #pipes and filters #process #statistics
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies (AD, SB, SM, NB, KR), pp. 926–931.
DATEDATE-2005-KumarLTW #multi #probability #process #statistics
A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching (YSK, JL, CT, JMW), pp. 770–775.
DATEDATE-2005-KumarTCJ #fault
Implicit and Exact Path Delay Fault Grading in Sequential Circuits (MMVK, ST, SC, RJ), pp. 990–995.
DATEDATE-2005-MartinelliD #bound #composition #set
Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition (AM, ED), pp. 430–431.
DATEDATE-2005-WangMDCM #analysis #embedded #energy #process #variability
Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules (HW, MM, WD, FC, KM), pp. 914–919.
SCAMSCAM-2005-BermudoKH #assembly #control flow #graph #re-engineering #source code
Control Flow Graph Reconstruction for Assembly Language Programs with Delayed Instructions (NB, AK, RNH), pp. 107–118.
SACSAC-2005-ZhengZOMF #clustering #network
Node clustering based on link delay in P2P networks (WZ, SZ, YO, FM, JF), pp. 744–749.
CAVCAV-2005-BozzanoBCJRRS #modulo theories #performance #satisfiability
Efficient Satisfiability Modulo Theories via Delayed Theory Combination (MB, RB, AC, TAJ, SR, PvR, RS), pp. 335–349.
DACDAC-2004-AgarwalDB #multi #statistics
Statistical gate delay model considering multiple input switching (AA, FD, DB), pp. 658–663.
DACDAC-2004-AgarwalSBLNV #analysis #metric
Variational delay metrics for interconnect timing analysis (KA, DS, DB, FL, SRN, SBKV), pp. 381–384.
DACDAC-2004-ChangHW
Re-synthesis for delay variation tolerance (SCC, CTH, KCW), pp. 814–819.
DACDAC-2004-KouroussisAN #power management #worst-case
Worst-case circuit delay taking into account power supply variations (DK, RA, FNN), pp. 652–657.
DACDAC-2004-OrshanskyB #analysis #correlation #performance #statistics
Fast statistical timing analysis handling arbitrary delay correlations (MO, AB), pp. 337–342.
DACDAC-2004-SultaniaSS #trade-off
Tradeoffs between date oxide leakage and delay for dual Tox circuits (AKS, DS, SSS), pp. 761–766.
DACDAC-2004-WangMCA #learning #on the
On path-based learning and its applications in delay test and diagnosis (LCW, TMM, KTC, MSA), pp. 492–497.
DATEDATE-v1-2004-PadmanabanT #fault #identification #performance #using
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults (SP, ST), pp. 50–55.
DATEDATE-v1-2004-Wang #learning #simulation #validation
Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation (LCW), pp. 692–695.
DATEDATE-v2-2004-KahngMR #named
Boosting: Min-Cut Placement with Improved Signal Delay (ABK, ILM, SR), pp. 1098–1103.
DATEDATE-v2-2004-LampropoulosAR #using
Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique (ML, BMAH, PMR), pp. 1372–1373.
DATEDATE-v2-2004-RahimiBD #adaptation #optimisation
Timing Correction and Optimization with Adaptive Delay Sequential Element (KR, SB, CD), p. 1416.
DATEDATE-v2-2004-RosselloS
A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk (JLR, JS), pp. 954–961.
DATEDATE-v2-2004-WangLC #fault #hardware #hybrid #testing
Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets (SW, XL, STC), pp. 1296–1301.
CHICHI-2004-GutwinBDFVG #collaboration
Revealing delay in collaborative environments (CG, SB, JD, MF, IV, CG), pp. 503–510.
ICEISICEIS-v2-2004-CuellarFJN #adaptation #network #predict
An Adaptable Time-Delay Neural Network to Predict the Spanish Economic Indebtedness (MPC, WF, MdCPJ, RPP, MAN), pp. 457–460.
KRKR-2004-CadoliM #automation #constraints #specification
Automated Reformulation of Specifications by Safe Delay of Constraints (MC, TM), pp. 388–398.
SACSAC-2004-MinOAK #communication #network
Communication delay in hypercubic networks with LRD traffic (GM, MOK, IUA, DDK), pp. 347–351.
DACDAC-2003-AgarwalBZV #bound #refinement #statistics
Computation and Refinement of Statistical Bounds on Circuit Delay (AA, DB, VZ, SBKV), pp. 348–353.
DACDAC-2003-AlpertLKD #metric #using
Delay and slew metrics using the lognormal distribution (CJA, FL, CVK, AD), pp. 382–385.
DACDAC-2003-BozorgzadehGTS #graph #integer
Optimal integer delay budgeting on directed acyclic graphs (EB, SG, AT, MS), pp. 920–925.
DACDAC-2003-CroixW #analysis #modelling #using
Blade and razor: cell and interconnect delay analysis using current-based models (JFC, DFW), pp. 386–389.
DACDAC-2003-KrsticWCLM #fault #modelling #statistics
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models (AK, LCW, KTC, JJL, TMM), pp. 668–673.
DACDAC-2003-RamachandranJ #embedded #energy #memory management #named #performance
Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processing (AR, MFJ), pp. 137–142.
DACDAC-2003-ThudiB
Non-iterative switching window computation for delay-noise (BT, DB), pp. 390–395.
DACDAC-2003-YehM
Delay budgeting in sequential circuit with application on FPGA placement (CYY, MMS), pp. 202–207.
DATEDATE-2003-HuangCW #nondeterminism
Global Wire Bus Configuration with Minimum Delay Uncertainty (LDH, HMC, DFW), pp. 10050–10055.
DATEDATE-2003-KrsticWCLA #fault #modelling #statistics
Delay Defect Diagnosis Based Upon Statistical Timing Models — The First Step (AK, LCW, KTC, JJL, MSA), pp. 10328–10335.
DATEDATE-2003-OhtakeOF #algorithm #fault #generative #testing #using
A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms (SO, KO, HF), pp. 10310–10315.
DATEDATE-2003-PadmanabanT #fault
Non-Enumerative Path Delay Fault Diagnosis (SP, ST), pp. 10322–10327.
DATEDATE-2003-SeidlEJ #using
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information (US, KE, FMJ), pp. 10770–10777.
DATEDATE-2003-VelenisPF #network #nondeterminism #performance
Reduced Delay Uncertainty in High Performance Clock Distribution Networks (DV, MCP, EGF), pp. 10068–10075.
DATEDATE-2003-XuN #fault #testing
Delay Fault Testing of Core-Based Systems-on-a-Chi (QX, NN), pp. 10744–10752.
VLDBVLDB-2003-Kuhn #database #semistructured data
The Zero-Delay Data Warehouse: Mobilizing Heterogeneous Databases (EK), pp. 1035–1040.
SACSAC-2003-GassendCDD #authentication
Delay-Based Circuit Authentication and Applications (BG, DEC, MvD, SD), pp. 294–301.
SACSAC-2003-SalveminiSSSZZ #architecture #embedded #energy #performance #trade-off
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems (LS, MS, DS, CS, VZ, RZ), pp. 672–678.
CADECADE-2003-GanzingerS #equivalence #normalisation #reasoning
Superposition with Equivalence Reasoning and Delayed Clause Normal Form Transformation (HG, JS), pp. 335–349.
DACDAC-2002-ChenMB02a
Coping with buffer delay change due to power and ground noise (LHC, MMS, FB), pp. 860–865.
DACDAC-2002-ChoiRD #generative
Timed pattern generation for noise-on-delay calculation (SHC, KR, FD), pp. 870–873.
DACDAC-2002-LiouKWC #analysis #performance #statistics #testing #validation
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation (JJL, AK, LCW, KTC), pp. 566–569.
DACDAC-2002-LiouWCDMKW #fault #multi #performance #testing #using
Enhancing test efficiency for delay fault testing using multiple-clocked schemes (JJL, LCW, KTC, JD, MRM, RK, TWW), pp. 371–374.
DACDAC-2002-MurugavelR #estimation #modelling #petri net
Petri net modeling of gate and interconnect delays for power estimation (AKM, NR), pp. 455–460.
DACDAC-2002-Sheehan #predict
Osculating Thevenin model for predicting delay and slew of capacitively characterized cells (BNS), pp. 866–869.
DACDAC-2002-ZengAA #identification #using
False timing path identification using ATPG techniques and delay-based information (JZ, MSA, JAA), pp. 562–565.
DATEDATE-2002-NayakHCB
Accurate Area and Delay Estimators for FPGAs (AN, MH, ANC, PB), pp. 862–869.
DATEDATE-2002-PadmanabanT #fault #multi
Exact Grading of Multiple Path Delay Faults (SP, ST), pp. 84–88.
DATEDATE-2002-PomeranzR #fault #multi #set #using
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults (IP, SMR), pp. 722–729.
DATEDATE-2002-SulimmaKNV #constant
Improving Placement under the Constant Delay Model (KS, WK, IN, LPPPvG), pp. 677–682.
DLTDLT-2002-DoL #bound #on the #product line
On a Family of Codes with Bounded Deciphering Delay (DLV, IL), pp. 369–380.
KRKR-2002-BaralST
A Transition Function Based Characterization of Actions with Delayed and Continuous Effects (CB, TCS, LCT), pp. 291–302.
SACSAC-2002-ShahrabiOM #communication #network
Communication delay in wormhole-routed torus networks (AS, MOK, LMM), pp. 825–829.
ASPLOSASPLOS-2002-KimBK #adaptation
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches (CK, DB, SWK), pp. 211–222.
HPCAHPCA-2002-YangPFV #design #energy
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay (SHY, MDP, BF, TNV), pp. 151–161.
DACDAC-2001-BaiBH #analysis #power management
Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits (GB, SB, INH), pp. 295–300.
DACDAC-2001-ChenGB
A New Gate Delay Model for Simultaneous Switching and Its Applications (LCC, SKG, MAB), pp. 289–294.
DACDAC-2001-KimJSLK #optimisation #using
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique (KWK, SOJ, PS, CLL, SMK), pp. 732–737.
DACDAC-2001-LuCYP #metric #modelling
Min/max On-Chip Inductance Models and Delay Metrics (YCL, MC, TY, LTP), pp. 341–346.
DACDAC-2001-McDonaldB #analysis #simulation #using
Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis (CBM, REB), pp. 283–288.
DACDAC-2001-SirichotiyakulBOLZZ #modelling #worst-case
Driver Modeling and Alignment for Worst-Case Delay Noise (SS, DB, CO, RL, VZ, JZ), pp. 720–725.
DATEDATE-2001-ChangHM #functional #optimisation #symmetry #using
In-place delay constrained power optimization using functional symmetries (CWJC, BH, MMS), pp. 377–382.
DATEDATE-2001-GaoW #algorithm #graph #modelling
A graph based algorithm for optimal buffer insertion under accurate delay models (YG, DFW), pp. 535–539.
DATEDATE-2001-GarnicaLH #power management #pseudo
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits (OG, JL, RH), p. 810.
DATEDATE-2001-Ruiz-de-ClavijoJBAV #logic #named
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model (PRdC, JJC, MJB, AJA, MV), pp. 467–471.
DATEDATE-2001-SarkarK #constraints
Repeater block planning under simultaneous delay and transition time constraints (PS, CKK), pp. 540–545.
AdaEuropeAdaEurope-2001-ZamoranoRP #ada #implementation #kernel #realtime
Implementing Ada.Real_Time.Clock and Absolute Delays in Real-Time Kernels (JZ, JFR, JAdlP), pp. 317–327.
HPCAHPCA-2001-PehD #architecture #pipes and filters
A Delay Model and Speculative Architecture for Pipelined Routers (LSP, WJD), pp. 255–266.
HPDCHPDC-2001-KrintzC
Reducing Delay with Dynamic Selection of Compression Formats (CK, BC), p. 266–?.
DACDAC-2000-Hassoun #analysis #bound #using
Critical path analysis using a dynamically bounded delay model (SH), pp. 260–265.
DACDAC-2000-KetkarKS #modelling
Convex delay models for transistor sizing (MK, KK, SSS), pp. 655–660.
DACDAC-2000-PomeranzR #fault #on the
On diagnosis of pattern-dependent delay faults (IP, SMR), pp. 59–62.
DATEDATE-2000-CiricYS #implementation #logic #using
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic (JC, GY, CS), pp. 277–282.
DATEDATE-2000-GaoW #using
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model (YG, DFW), pp. 512–516.
DATEDATE-2000-HiroseY #reduction
A Bus Delay Reduction Technique Considering Crosstalk (KH, HY), pp. 441–445.
DATEDATE-2000-JacobsB #statistics #using
Gate Sizing Using a Statistical Delay Model (ETAFJ, MRCMB), pp. 283–290.
DATEDATE-2000-JosephsF #interface #specification #synthesis
Delay-Insensitive Interface Specification and Synthesis (MBJ, DPF), pp. 169–173.
DATEDATE-2000-KimWSS #fault #incremental #on the #satisfiability #testing
On Applying Incremental Satisfiability to Delay Fault Testing (JK, JW, KAS, JPMS), pp. 380–384.
DATEDATE-2000-KumthekarS #logic #optimisation #reduction
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs (BK, FS), pp. 202–207.
DATEDATE-2000-LiuAW #constraints
Meeting Delay Constraints in DSM by Minimal Repeater Insertion (IML, AA, DFW), pp. 436–440.
DATEDATE-2000-ParkK #bound #design #detection #fault
A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects (SP, TK), pp. 458–462.
DATEDATE-2000-SuCHCL #metric
All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses (CS, YTC, MJH, GNC, CLL), pp. 527–531.
DATEDATE-2000-TsiatouhasHAN #fault #self #testing
A Versatile Built-In Self-Test Scheme for Delay Fault Testing (YT, TH, AA, DN), p. 756.
FoSSaCSFoSSaCS-2000-BaierS #bisimulation #probability
Norm Functions for Probabilistic Bisimulations with Delays (CB, MS), pp. 1–16.
CSCWCSCW-2000-HerbslebMFG #collaboration #dependence #distance
Distance, dependencies, and delay in a global collaboration (JDH, AM, TAF, REG), pp. 319–328.
HPCAHPCA-2000-RajwarKG #throughput
Improving the Throughput of Synchronization by Insertion of Delays (RR, AK, JRG), pp. 168–179.
DACDAC-1999-AlpertDQ
Buffer Insertion with Accurate Gate and Interconnect Delay Computation (CJA, AD, STQ), pp. 479–484.
DACDAC-1999-CongHX #performance
Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections (JC, YYH, SX), pp. 373–378.
DACDAC-1999-IsmailF
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits (YII, EGF), pp. 721–724.
DACDAC-1999-IsmailFN
Equivalent Elmore Delay for RLC Trees (YII, EGF, JLN), pp. 715–720.
DACDAC-1999-RoyBB #algorithm #constraints
An Approxmimate Algorithm for Delay-Constraint Technology Mapping (SR, KPB, PB), pp. 367–372.
DACDAC-1999-TabbaraBN #constraints #trade-off
Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints (AT, RKB, ARN), pp. 725–730.
DATEDATE-1999-BuhlerPKB #approach #performance #process #simulation #using
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach (MB, MP, KK, UGB), p. 459–?.
DATEDATE-1999-LiuPF
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits (XL, MCP, EGF), pp. 643–649.
DATEDATE-1999-NikolosVHT #embedded #fault #testing
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks (DN, HTV, TH, YT), pp. 112–116.
DATEDATE-1999-TragoudasM #fault #functional #tool support
ATPG Tools for Delay Faults at the Functional Level (ST, MKM), p. 631–?.
STOCSTOC-1999-AndrewsZ #requirements
Packet Routing with Arbitrary End-to-End Delay Requirements (MA, LZ), pp. 557–565.
HCIHCI-EI-1999-TakadaTS
Influence of Delay Time in Remote Camera Control (KT, HT, YS), pp. 421–425.
AdaSIGAda-1999-LundqvistA #ada #formal method
A formal model of the Ada Ravenscar tasking profile; delay until (KL, LA), pp. 15–21.
OOPSLAOOPSLA-1999-KrintzCH #java #using
Reducing Transfer Delay Using Java Class File Splitting and Prefetching (CK, BC, UH), pp. 276–291.
DACDAC-1998-AlpertDQ #optimisation
Buffer Insertion for Noise and Delay Optimization (CJA, AD, STQ), pp. 362–367.
DACDAC-1998-CongX
Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs (JC, SX), pp. 704–707.
DACDAC-1998-KayP #named #probability
PRIMO: Probability Interpretation of Moments for Delay Calculation (RK, LTP), pp. 463–468.
DACDAC-1998-KukimotoBS #graph
Delay-Optimal Technology Mapping by DAG Covering (YK, RKB, PS), pp. 348–351.
DACDAC-1998-NassifDH #modelling #robust #verification
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor (NN, MPD, DHH), pp. 230–235.
DACDAC-1998-NemaniN #estimation #perspective
Delay Estimation VLSI Circuits from a High-Level View (MN, FNN), pp. 591–594.
DATEDATE-1998-Catthoor #architecture #design #energy #performance
Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit Technology versus Design Methodology Solutions (FC), pp. 709–714.
DATEDATE-1998-ChandramouliWS #analysis #functional #named
AFTA: A Formal Delay Model for Functional Timing Analysis (VC, JW, KAS), pp. 350–355.
DATEDATE-1998-DagaOA
Temperature Effect on Delay for Low Voltage Applications (JMD, EO, DA), pp. 680–685.
PODSPODS-1998-ChristodoulakisZ #database #design
Data Base Design Principles for Striping and Placement of Delay-Sensitive Data on Disks (SC, FZ), pp. 69–78.
SIGMODSIGMOD-1998-UrhanFA #query
Cost Based Query Scrambling for Initial Delays (TU, MJF, LA), pp. 130–141.
STOCSTOC-1998-DoolyGS #theory and practice
TCP Dynamic Acknowledgment Delay: Theory and Practice (Extended Abstract) (DRD, SAG, SDS), pp. 389–398.
LICSLICS-1998-StarkS #analysis #automaton #composition #network #probability
Compositional Analysis of Expected Delays in Networks of Probabilistic I/O Automata (EWS, SAS), pp. 466–477.
DACDAC-1997-DartuP #worst-case
Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling (FD, LTP), pp. 46–51.
DACDAC-1997-WangVG #trade-off
An Investigation of Power Delay Trade-Offs on PowerPC Circuits (QW, SBKV, SG), pp. 425–428.
DATEEDTC-1997-Fishburn
Shaping a VLSI wire to minimize Elmore delay (JPF), pp. 244–251.
DATEEDTC-1997-GirodiasC #constraints #correlation #interface #logic programming #using #verification
Interface timing verification with delay correlation using constraint logic programming (PG, EC), pp. 12–19.
DATEEDTC-1997-ManichF #process
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model (SM, JF), pp. 597–602.
DATEEDTC-1997-SmeetsAEK #programmable #video
Delay management for programmable video signal processors (MLGS, EHLA, GE, EAdK), pp. 126–133.
ICALPICALP-1997-Bruyere #algorithm #bound
A Completion Algorithm for Codes with Bounded Synchronization Delay (VB), pp. 87–97.
HCIHCI-CC-1997-RoastS #framework #interface #towards
Towards a Framework for Managing Interface Delay (CR, JIAS), pp. 745–748.
HCIHCI-SEC-1997-GargRK #fault #modelling
Modeling the Sources and Consequences of Errors and Delays in Complex Systems (CG, VR, JWK), pp. 67–70.
HCIHCI-SEC-1997-SearsB #design #distributed #documentation #internet #multi
The Effect of Internet Delay on the Design of Distributed Multimedia Documents (AS, MSB), pp. 331–334.
HCIHCI-SEC-1997-SearsJB #internet #quality
The Effect of Internet Delay on the Perceived Quality of Information (AS, JAJ, MSB), pp. 335–338.
LOPSTRLOPSTR-1997-HeatonHK #analysis #logic programming #source code
Analysis of Logic Programs with Delay (AH, PMH, AK), pp. 148–167.
DACDAC-1996-ChandramouliS #modelling #proximity
Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time (VC, KAS), pp. 617–622.
DACDAC-1996-ChenCW96a
Optimal Wire-Sizing Formular Under the Elmore Delay Model (CPC, YPC, DFW), pp. 487–490.
DACDAC-1996-ChenG #fault #generative #satisfiability
A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts (CAC, SKG), pp. 209–214.
DACDAC-1996-DesaiY #cpu #design #simulation #using #verification
A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation (MPD, YTY), pp. 125–130.
DACDAC-1996-Gupta #analysis #constraints #embedded #execution
Analysis of Operation Delay and Execution Rate Constraints for Embedded Systems (RKG), pp. 601–604.
DACDAC-1996-LalgudiPP #effectiveness #optimisation #problem
Optimizing Systems for Effective Block-Processing: The k-Delay Problem (KNL, MCP, MP), pp. 714–719.
DACDAC-1996-LillisCLH #performance #trade-off
New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing (JL, CKC, TTYL, CYH), pp. 395–400.
DACDAC-1996-LimSPS #approach #estimation #process #statistics
A Statistical Approach to the Estimation of Delay Dependent Switching Activities in CMOS Combinational Circuits (YJL, KIS, HJP, MS), pp. 445–450.
DACDAC-1996-OhPP #bound #linear #programming #using
Constructing Lower and Upper Bounded Delay Routing Trees Using Linear Programming (JO, IP, MP), pp. 401–404.
DACDAC-1996-Sheehan #performance
An AWE Technique for Fast Printed Circuit Board Delays (BNS), pp. 539–543.
DACDAC-1996-ThakurWK #composition #multi
Delay Minimal Decomposition of Multiplexers in Technology Mapping (ST, DFW, SK), pp. 254–257.
DACDAC-1996-TutuianuDP #approximate
An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response (BT, FD, LTP), pp. 611–616.
ICMLICML-1996-Sebag #approach #bias
Delaying the Choice of Bias: A Disjunctive Version Space Approach (MS), pp. 444–452.
ICPRICPR-1996-DayP #generative #network #using
The generation of motion kinematics using a time-delay neural network (MJSD, JSP), pp. 545–549.
ICPRICPR-1996-PengB #learning #recognition
Delayed reinforcement learning for closed-loop object recognition (JP, BB), pp. 310–314.
HPDCHPDC-1996-VenugopalR #empirical #parallel
Impact of Delays in Parallel I/O System: An Empirical Study (CRV, SSSPR), pp. 490–499.
ICLPJICSLP-1996-Zhou #implementation #novel
A Novel Implementation Method of Delay (NFZ), pp. 97–111.
DACDAC-1995-GeloshS #layout #modelling #performance #tool support
Deriving Efficient Area and Delay Estimates by Modeling Layout Tools (DSG, DES), pp. 402–407.
DACDAC-1995-GuptaKTWP #bound
The Elmore Delay as a Bound for RC Trees with Generalized Input Signals (RG, BK, BT, JW, LTP), pp. 364–369.
DACDAC-1995-KarkowskiO
Retiming Synchronous Circuitry with Imprecise Delays (IK, RHJMO), pp. 322–326.
DACDAC-1995-LalgudiP #modelling #named #performance
DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling (KNL, MCP), pp. 304–309.
DACDAC-1995-LeeW #performance
A Performance and Routability Driven Router for FPGAs Considering Path Delays (YSL, ACHW), pp. 557–561.
DACDAC-1995-MeijsG
Delayed Frontal Solution for Finite-Element Based Resistance Extraction (NPvdM, AJvG), pp. 273–278.
DACDAC-1995-MenezesPP #optimisation
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization (NM, SP, LTP), pp. 690–695.
DACDAC-1995-Najm #correlation #estimation #feedback
Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits (FNN), pp. 612–617.
DACDAC-1995-NajmZ #process #worst-case
Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits (FNN, MYZ), pp. 623–627.
DACDAC-1995-Rao #analysis #distributed
Delay Analysis of the Distributed RC Line (VBR), pp. 370–375.
DACDAC-1995-RohfleischWA #analysis #logic #optimisation
Logic Clause Analysis for Delay Optimization (BR, BW, KA), pp. 668–672.
DACDAC-1995-SawkarT #clustering #multi
Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs (PS, DET), pp. 201–205.
DACDAC-1995-SparmannLCR #fault #identification #performance #robust
Fast Identification of Robust Dependent Path Delay Faults (US, DL, KTC, SMR), pp. 119–125.
STOCSTOC-1995-Harchol-BalterW #bound #network
Bounding delays in packet-routing networks (MHB, DW), pp. 248–257.
STOCSTOC-1995-RaghavanU #probability
Stochastic contention resolution with short delays (PR, EU), pp. 229–237.
ICMLICML-1995-MoriartyM #evolution #learning #performance
Efficient Learning from Delayed Rewards through Symbiotic Evolution (DEM, RM), pp. 396–404.
ICLPILPS-1995-MarchioriT #logic programming #proving #source code #termination
Proving Termination of Logic Programs with Delay Declarations (EM, FT), pp. 447–461.
DACDAC-1994-BoeseKMR
Rectilinear Steiner Trees with Minimum Elmore Delay (KDB, ABK, BAM, GR), pp. 381–386.
DACDAC-1994-ChengC #fault #generative #quality #testing
Generation of High Quality Non-Robust Tests for Path Delay Faults (KTC, HCC), pp. 365–369.
DACDAC-1994-DartuMQP #performance
A Gate-Delay Model for high-Speed CMOS Circuits (FD, NM, JQ, LTP), pp. 576–580.
DACDAC-1994-FangG #low cost #testing
Clock Grouping: A Low Cost DFT Methodology for Delay Testing (WCF, SKG), pp. 94–99.
DACDAC-1994-HenftlingWA #fault #simulation
Path Hashing to Accelerate Delay Fault Simulation (MH, HCW, KA), pp. 522–526.
DACDAC-1994-HeraguBA #fault #performance
An Efficient Path Delay Fault Coverage Estimator (KH, MLB, VDA), pp. 516–521.
DACDAC-1994-JyuM #design #logic #modelling #statistics #synthesis
Statistical Delay Modeling in Logic Design and Synthesis (HFJ, SM), pp. 126–130.
DACDAC-1994-KahngM #analysis #equation #using
Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model (ABK, SM), pp. 563–569.
DACDAC-1994-KannanSF #algorithm #optimisation
A Methodology and Algorithms for Post-Placement Delay Optimization (LNK, PS, HGF), pp. 327–332.
DACDAC-1994-PomeranzR #combinator #fault #scalability #using
Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points (IP, SMR), pp. 358–364.
DACDAC-1994-Sapatnekar #optimisation
RC Interconnect Optimization Under the Elmore Delay Model (SSS), pp. 387–391.
DACDAC-1994-VittalM #design #using
Minimal Delay Interconnect Design Using Alphabetic Trees (AV, MMS), pp. 392–396.
DATEEDAC-1994-AjuhaM #reduction
Delay Reduction by Segment Substitution (HA, PRM), pp. 82–86.
DATEEDAC-1994-ChenG #generative #testing
BIST Test Pattern Generators for Stuck-Open and Delay Testing (CAC, SKG), pp. 289–296.
DATEEDAC-1994-DepuydtGGM #graph #optimisation #pipes and filters #scheduling
Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization (FD, WG, GG, HDM), pp. 490–494.
DATEEDAC-1994-DumasGLP #effectiveness #fault
Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis (DD, PG, CL, SP), pp. 518–523.
DATEEDAC-1994-FummiSS #approach #fault #functional #generative #testing
A Functional Approach to Delay Faults Test Generation for Sequential Circuits (FF, DS, MS), pp. 51–57.
DATEEDAC-1994-KeM #synthesis
Synthesis of Delay-Verifiable Two-Level Circuits (WK, PRM), pp. 297–301.
DATEEDAC-1994-KunzmannB #fault
Gate-Delay Fault Test with Conventional Scan-Design (AK, FB), pp. 524–528.
DATEEDAC-1994-LinCL #fault #named #performance
TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator (MCL, JEC, CLL), pp. 508–512.
DATEEDAC-1994-VuksicF #approach #fault #testing
A New BIST Approach for Delay Fault Testing (AV, KF), pp. 284–288.
DATEEDAC-1994-WittmannH #identification #optimisation #performance #testing
Efficient Path Identification for Delay Testing — Time and Space Optimization (HCW, MH), pp. 513–517.
CCCC-1994-ErtlK #exception #execution
Delayed Exceptions — Speculative Execution of Trapping Instructions (MAE, AK), pp. 158–171.
HPDCHPDC-1994-PramanickP #distributed #evaluation #fault #problem #quality
Distributed Solutions to the Delay Fault Test Quality Evaluation Problem (IP, AKP), pp. 177–185.
DACDAC-1993-ChakrabortyAB #design #fault #testing
Design for Testability for Path Delay faults in Sequential Circuits (TJC, VDA, MLB), pp. 453–457.
DACDAC-1993-ChakradharDPR #optimisation #using
Sequential Circuit Delay optimization Using Global Path Delays (STC, SD, MP, SGR), pp. 483–489.
DACDAC-1993-CongLZ #design #distributed
Performance-Driven Interconnect Design Based on Distributed RC Delay Model (JC, KSL, DZ), pp. 606–611.
DACDAC-1993-LamBS #modelling #using
Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions (WKCL, RKB, ALSV), pp. 128–134.
DACDAC-1993-LamSBS #fault #performance #trade-off
Delay Fault Coverage and Performance Tradeoffs (WKCL, AS, RKB, ALSV), pp. 446–452.
DACDAC-1993-PomeranzRU #fault #generative #named #testing
NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits (IP, SMR, PU), pp. 439–445.
DACDAC-1993-RajaramanW #clustering
Optimal Clustering for Delay Minimization (RR, DFW), pp. 309–314.
STOCSTOC-1993-Goldberg #algorithm #graph #polynomial #product line
Polynomial space polynomial delay algorithms for listing families of graphs (LAG), pp. 218–225.
HCIHCI-ACS-1993-Caldwell #constraints
Situational and Informational Constraints Affecting Communications with 1-1000 Second Transmission Delays (BSC), pp. 167–172.
HCIHCI-SHI-1993-Caldwell93a #feedback #social
Social Implications of Feedback and Delay Characteristics in Electronic Communications Usage (BSC), pp. 843–848.
PPDPPLILP-1993-Boye #functional #logic programming #source code
Avoiding Dynamic Delays in Functional Logic Programs (JB), pp. 12–27.
SACSAC-1993-ShenDU #data flow #predict
Packet Delay Prediction in Datagram Mesh Systems (ZS, PGD, LU), pp. 539–545.
CAVCAV-1993-AlurCH #realtime
Computing Accumulated Delays in Real-time Systems (RA, CC, TAH), pp. 181–193.
CAVCAV-1993-Halbwachs #analysis #source code
Delay Analysis in Synchronous Programs (NH), pp. 333–346.
DACDAC-1992-BhattacharyaAA #fault #generative #testing #using
Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions (DB, PA, VDA), pp. 159–164.
DACDAC-1992-ChakrabortyAB #fault #generative #logic #modelling #random #testing
Delay Fault Models and Test Generation for Random Logic Sequential Circuits (TJC, VDA, MLB), pp. 165–172.
DACDAC-1992-ChaudharyP #algorithm #constraints
A Near Optimal Algorithm for Technology Mapping Minimizing Area under Delay Constraints (KC, MP), pp. 492–498.
DACDAC-1992-DevadasKMW #logic #verification
Certified Timing Verification and the Transition Delay of a Logic Circuit (SD, KK, SM, ARW), pp. 549–555.
DACDAC-1992-GirardLP #approach #novel
A Novel Approach to Delay-Fault Diagnosis (PG, CL, SP), pp. 357–360.
DACDAC-1992-Jones #incremental
Zero Delay versus Positive Delay in an Incremental Switch-Level Simulator (LGJ), pp. 424–427.
DACDAC-1992-LeeM #logic #multi #simulation
Two New Techniques for Compiled Multi-Delay Logic Simulation (YSL, PMM), pp. 420–423.
DACDAC-1992-PomeranzR #testing
At-Speed Delay Testing of Synchronous Sequential Circuits (IP, SMR), pp. 177–181.
DACDAC-1992-RundensteinerG #functional #optimisation #synthesis #using
Functional Synthesis Using Area and Delay Optimization (EAR, DG), pp. 291–296.
DACDAC-1992-SaldanhaBS #equivalence #generative #robust #testing
Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation (AS, RKB, ALSV), pp. 173–176.
DACDAC-1992-SaldanhaBS92a #algorithm #revisited
Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited (AS, RKB, ALSV), pp. 245–248.
DACDAC-1992-SawkarT #array #programmable
Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays (PS, DET), pp. 368–373.
SIGMODSIGMOD-1992-AgrawalAJ #database #protocol #realtime #using
Using Delayed Commitment in Locking Protocols for Real-Time Databases (DA, AEA, RJ), pp. 104–113.
CHICHI-1992-TealR #performance
A performance model of system delay and user strategy selection (SLT, AIR), pp. 295–305.
CAVCAV-1992-ProbstL #automaton #behaviour #constraints #verification
Verifying Timed Behavior Automata with Nonbinary Delay Constraints (DKP, HFL), pp. 123–136.
DACDAC-1991-BeerelM #testing
Testability of Asynchronous Timed Control Circuits with Delay Assumptions (PAB, THYM), pp. 446–451.
DACDAC-1991-ChengDK #design #generative #robust #standard #synthesis #testing
Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology (KTC, SD, KK), pp. 80–86.
DACDAC-1991-HuHB #pipes and filters
Minimizing the Number of Delay Buffers in the Synchronization of Pipelined Systems (XH, RGH, SCB), pp. 758–763.
DACDAC-1991-MaoC #design #fault
Correlation-Reduced Scan-path Design To Improve Delay Fault Coverage (WM, MDC), pp. 73–79.
DACDAC-1991-MattesWBD
Propagation Delay Calculation for Interconnection Nets on Printed Circuit Boards by Reflected Waves (HM, WW, GB, RD), pp. 567–572.
DACDAC-1991-WilliamsUM #network #testing
The Interdependence Between Delay-Optimization of Synthesized Networks and Testing (TWW, BU, MRM), pp. 87–92.
DACDAC-1991-WuL #fault #probability #testing
A Probabilistic Testability Measure for Delay Faults (WCW, CLL), pp. 440–445.
DACDAC-1991-WuR #effectiveness #evaluation
Delay Test Effectiveness Evaluation of LSSD-Based VLSI Vogic Circuits (DMW, CER), pp. 291–295.
PLDIPLDI-1991-ProebstingF #architecture #linear #scheduling
Linear-Time, Optimal Code Scheduling for Delayed-Load Architectures (TAP, CNF), pp. 256–267.
ICALPICALP-1991-HonkalaS #ambiguity #bound #morphism
L Morphisms: Bounded Delay and Regularity of Ambiguity (JH, AS), pp. 566–574.
CAVCAV-1991-Courcoubetis #problem #realtime
Minimum and Maximum Delay Problems in Real-Time Systems (CC), pp. 399–409.
CAVCAV-1991-Goldschlag #liveness #safety #verification
Mechanically Verifying Safety and Liveness Properties of Delay Insensitive Circuits (DMG), pp. 354–364.
DACDAC-1990-DevadasK #logic #optimisation #robust #synthesis
Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits (SD, KK), pp. 221–227.
DACDAC-1990-DonathNABHKLM #using
Timing Driven Placement Using Complete Path Delays (WED, RJN, BKA, SEB, SYH, JMK, PL, RIM), pp. 84–89.
DACDAC-1990-KeutzerMS
Is Redundancy Necessary to Reduce Delay (KK, SM, AS), pp. 228–234.
DACDAC-1990-LinMK #design #optimisation #standard
Delay and Area Optimization in Standard-Cell Design (SL, MMS, ESK), pp. 349–352.
DACDAC-1990-MaoC #fault #testing
A Variable Observation Time Method for Testing Delay Faults (WM, MDC), pp. 728–731.
DACDAC-1990-MaurerW #simulation
Techniques for Unit-Delay Compiled Simulation (PMM, ZW), pp. 480–484.
DACDAC-1990-ParkM #generative #logic #performance #testing
An Efficient Delay Test Generation System for Combinational Logic Circuits (ESP, MRM), pp. 522–528.
ESOPESOP-1990-SchreyePRB #constraints #implementation #logic programming #prolog
Implementing Finite-domain Constraint Logic Programming on Top of a Prolog-System with Delay-mechanism (DDS, DP, JR, MB), pp. 106–117.
CAVCAV-1990-JosephsU #algebra
An Algebra for Delay-Insensitive Circuits (MBJ, JTU), pp. 343–352.
DACDAC-1989-CahnK #clustering #network
Computing Signal Delay in General RC Networks by Tree/Link Partitioning (PKC, KK), pp. 485–490.
DACDAC-1989-FujiharaSIY #automation #named #optimisation #performance
DYNAJUST: An Efficient Automatic Routing Technique Optimizing Delay Conditions (YF, YS, YI, MY), pp. 791–794.
DACDAC-1989-GaiottiDR #estimation #worst-case
Worst-case Delay Estimation of Transistor Groups (SG, MD, NCR), pp. 491–495.
DACDAC-1989-GloverM #approach #fault #testing
A Deterministic Approach to Adjacency Testing for Delay Faults (CTG, MRM), pp. 351–356.
DACDAC-1989-MaoC #fault #testing
A Simplified Six-waveform Type Method for Delay Fault Testing (WM, MDC), pp. 730–733.
DACDAC-1989-PrasitjutrakulK #approach #programming
Path-Delay Constrained Floorplanning: A Mathematical Programming Approach for Initial Placement (SP, WJK), pp. 364–369.
DACDAC-1989-SchulzFF #fault #parallel #simulation
Parallel Pattern Fault Simulation of Path Delay Faults (MHS, FF, KF), pp. 357–363.
ICALPICALP-1989-Bruyere #finite
Completion of Finite Codes with Finite Deciphering Delay (VB), pp. 151–163.
SOSPSOSP-1989-BarkleyL #bound #lazy evaluation
A Lazy Buddy System Bounded by Two Coalescing Delays per Class (REB, TPL), pp. 167–176.
DACDAC-1988-ChangCS #performance
An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits (FCC, CFC, PS), pp. 282–287.
DACDAC-1988-GloverM #fault #generative #testing
A Method of Delay Fault Test Generation (CTG, MRM), pp. 90–95.
DACDAC-1988-SaabYH #modelling
Delay Modeling and Time of Bipolar Digital Circuits (DGS, ATY, INH), pp. 288–293.
CCCCHSC-1988-Alblas
Attributed Tree Transformations with Delayed and Smart Re-Evaluation (HA), pp. 160–174.
DACDAC-1987-CanrightH #logic
Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic (REC, ARH), pp. 133–139.
DACDAC-1987-HofmannK #logic #optimisation
Delay Optimization of Combinational Static CMOS Logic (MH, JKK), pp. 125–132.
DACDAC-1986-Adler #multi #named
SIMMOS: a multiple-delay switch-level simulator (DA), pp. 159–163.
DACDAC-1986-HwangKN #modelling #verification
An accuration delay modeling technique for switch-level timing verification (SHH, YHK, ARN), pp. 227–233.
DACDAC-1986-KishidaSIIH #logic
A delay test system for high speed logic LSI’s (KK, FS, YI, SI, TH), pp. 786–790.
DACDAC-1986-OgawaISTKYC #algorithm #optimisation #performance
Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs (YO, TI, YS, HT, TK, KY, KC), pp. 404–410.
DACDAC-1986-PincusD #reduction #using
Delay reduction using simulated annealing (JDP, AMD), pp. 690–695.
DACDAC-1986-ToyoshimaTMHHKT #analysis #design #effectiveness #scalability
An effective delay analysis system for a large scale computer design (RT, YT, KM, HH, MH, RK, KT), pp. 398–403.
VLDBVLDB-1986-SarinKS #database #process #using
Using History Information to Process Delayed Database Updates (SKS, CWK, JES), pp. 71–78.
DACDAC-1985-RajanT #synthesis
Synthesis by delayed binding of decisions (JVR, DET), pp. 367–373.
STOCSTOC-1985-Aggarwal #modelling #trade-off
Tradeoffs for VLSI Models with Subpolynomial Delay (AA), pp. 59–68.
DACDAC-1984-EtiembleADB #algorithm #evaluation
Micro-computer oriented algorithms for delay evaluation of MOS gates (DE, VA, NHD, JCB), pp. 358–364.
DACDAC-1984-GeusRRW #analysis #named
IDA: Interconnect delay analysis for integrated circuits (AJdG, JBR, MR, GW), pp. 536–541.
DACDAC-1984-GlasserH #optimisation
Delay and power optimization in VLSI circuits (LAG, LH), pp. 529–535.
DACDAC-1984-Ousterhout #modelling
Switch-level delay models for digital MOS VLSI (JKO), pp. 542–548.
DACDAC-1983-OkazakiMY #multi
A multiple media delay simulator for MOS LSI circuits (KO, TM, TY), pp. 279–285.
DACDAC-1983-TamuraON #analysis #layout
Path delay analysis for hierarchical building block layout system (ET, KO, TN), pp. 403–410.
ICALPICALP-1983-ChoffrutK #bound #morphism #testing
Test Sets for Morphisms with Bounded Delay (CC, JK), pp. 118–127.
DACDAC-1982-BeningLAS #analysis #logic #network
Developments in logic network path delay analysis (LB, TAL, CRA, JES), pp. 605–615.
DACDAC-1982-NomuraSTAY #verification
Timing verification system based on delay time hierarchical nature (MN, SS, NT, TA, AY), pp. 622–628.
DACDAC-1982-Putatunda #automation #named
Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips (RP), pp. 616–621.
VLDBVLDB-1982-Lafue #dependence #semantics
Semantic Integrity Dependencies and Delayed Integrity Checking (GMEL), pp. 292–299.
DACDAC-1981-KamikawaiYCFT
A critical path delay check system (RK, MY, TC, KF, YT), pp. 118–123.
DACDAC-1981-PenfieldR #network
Signal delay in RC tree networks (PPJ, JR), pp. 613–617.
DACDAC-1980-NhamB #multi
A multiple delay simulator for MOS LSI circuits (HNN, AKB), pp. 610–617.
DACDAC-1978-KoppelSP #logic #performance
A high performance delay calculation software system for MOSFET digital logic chips (AK, SS, PP), pp. 405–417.
POPLPOPL-1978-GuibasW #compilation #evaluation
Compilation and Delayed Evaluation in APL (LJG, DKW), pp. 1–8.
DACDAC-1977-HsiehRVD #generative #testing
Delay test generation (ERH, RAR, LJV, WTD), pp. 486–491.
DACDAC-1977-StoreyB #simulation
Delay test simulation (TMS, JWB), pp. 492–494.
DACDAC-1976-ChicoixPG #network #scalability #simulation
An accurate time delay model for large digital network simulation (CC, JP, NG), pp. 54–60.
DACDAC-1974-ThompsonSBP #analysis #fault #simulation #using
Timing analysis for digital fault simulation using assignable delays (EWT, SAS, NB, RP), pp. 266–272.
DACDAC-1973-PillingS #logic #predict
Computer-aided prediction of delays in LSI logic systems (DJP, HBS), pp. 182–186.
DACDAC-1972-Lewis #bound #detection #logic #simulation
Hazard detection by a quinary simulation of logic devices with bounded propagation delays (DWL), pp. 157–164.
ICALPICALP-1972-HoschL #finite
Finite Delay Solutions for Sequential Conditions (FAH, LHL), pp. 45–60.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.