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Collaborated with:
S.K.Rajamani S.A.Seshia M.Costa A.Lal N.P.Lopes K.Vaswani
Talks about:
methodolog (1) verifi (1) region (1) oblivi (1) design (1) comput (1) compil (1) access (1) verif (1) secur (1)

Person: Rohit Sinha 0001

DBLP DBLP: 0001:Rohit_Sinha

Contributed to:

ESEC/FSE 20172017
PLDI 20162016

Wrote 2 papers:

ESEC-FSE-2017-0001RS #compilation #verification
A compiler and verifier for page access oblivious computation (RS0, SKR, SAS), pp. 649–660.
PLDI-2016-0001CLLRSV #design #verification
A design and verification methodology for secure isolated regions (RS0, MC, AL, NPL, SKR, SAS, KV), pp. 665–681.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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