Travelled to:1 × USA
Collaborated with:H.Fuketa T.Yasufuku M.Takamiya M.Nomura H.Shinohara T.Sakurai
Talks about:minimum (1) express (1) voltag (1) logic (1) estim (1) close (1) oper (1) gate (1) form (1) dmin (1)
Person: Satoshi Iida
DBLP: Iida:Satoshi
Contributed to:
2011Wrote 1 papers:
- DAC-2011-FuketaIYTNSS #logic
- A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates (HF, SI, TY, MT, MN, HS, TS), pp. 984–989.