BibSLEIGH — gate stem

Used together with:

power (77)
level (54)
circuit (50)
design (47)
base (41)

Stem gate$ (all stems)

303 papers:

ECSA-2015-Jansen #architecture #challenge #ecosystem #interface: Opening the Ecosystem Flood Gates: Architecture Challenges of Opening Interfaces Within a Product Portfolio (SJ), pp. 121–136.
DAC-2015-ChiangCLJ #design #power management #scalability: Scalable sequence-constrained retention register minimization in power gating design (TWC, KHC, YTL, JHRJ), p. 6.
DAC-2015-CiesielskiYBLR #verification: Verification of gate-level arithmetic circuits by function extraction (MJC, CY, WB, DL, AR), p. 6.
DAC-2015-DaiKB #equivalence: Sequential equivalence checking of clock-gated circuits (YYD, KYK, RKB), p. 6.
DAC-2015-RoyLUP #multi #named #optimisation #paradigm #performance: OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions (SR, DL, JU, DZP), p. 6.
DAC-2015-TashjianD #identification #on the #using: On using control signals for word-level identification in a gate-level netlist (ET, AD), p. 6.
DATE-2015-CakirM #clustering #correlation #detection #hardware #using: Hardware Trojan detection for gate-level ICs using signal correlation based clustering (BÇ, SM), pp. 471–476.
DATE-2015-CalayirDWP #multi #programmable: Analog neuromorphic computing enabled by multi-gate programmable resistive devices (VC, MD, JAW, LP), pp. 928–931.
DATE-2015-CasagrandeR #algorithm #fuzzy #game studies #named #novel #optimisation #robust: GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games (TC, NR), pp. 677–682.
DATE-2015-LiuHDCPKKTR: Clock domain crossing aware sequential clock gating (JL, MSH, KTD, JYC, JP, MK, MK, NT, AR), pp. 1–6.
DATE-2015-LiXWNP #fine-grained #multi #power management #reduction #using: Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique (JL, QX, YW, SN, MP), pp. 1579–1582.
DATE-2015-MirhosseiniSFMS #energy #network: An energy-efficient virtual channel power-gating mechanism for on-chip networks (AM, MS, AF, MM, HSA), pp. 1527–1532.
DATE-2015-OyaSYT #classification #identification: A score-based classification method for identifying hardware-trojans at gate-level netlists (MO, YS, MY, NT), pp. 465–470.
DATE-2015-ShutoYS #architecture #case study #comparative #using: Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology (YS, SY, SS), pp. 866–871.
DATE-2015-WangWXWWYDLMW #adaptation #process: Adaptively tolerate power-gating-induced power/ground noise under process variations (ZW, XW, JX, XW, ZW, PY, LHKD, HL, RKVM, ZW), pp. 483–488.
LATA-2015-AmanoS #bound #multi #polynomial: A Nonuniform Circuit Class with Multilayer of Threshold Gates Having Super Quasi Polynomial Size Lower Bounds Against NEXP (KA, AS), pp. 461–472.
CSCW-2015-DantecF #research: Strangers at the Gate: Gaining Access, Building Rapport, and Co-Constructing Community-Based Research (CALD, SF), pp. 1348–1358.
ICML-2015-ChungGCB #feedback #network: Gated Feedback Recurrent Neural Networks (JC, ÇG, KC, YB), pp. 2067–2075.
HPCA-2015-AroraMPJT #behaviour #benchmark #comprehension #cpu #gpu #metric #power management: Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems (MA, SM, IP, NJ, DMT), pp. 366–377.
HPCA-2015-ChenZPP #towards: Power punch: Towards non-blocking power-gating of NoC routers (LC, DZ, MP, TMP), pp. 378–389.
SAT-2015-IserMS #recognition: Recognition of Nested Gates in CNF Formulas (MI, NM, CS), pp. 255–271.
DAC-2014-ChangJC #configuration management #functional #using: Functional ECO Using Metal-Configurable Gate-Array Spare Cells (HYC, IHRJ, YWC), p. 6.
DAC-2014-SullivanBZZJ #functional #hardware #identification #named: FIGHT-Metric: Functional Identification of Gate-Level Hardware Trustworthiness (DS, JB, GZ, SZ, YJ), p. 4.
DATE-2014-AhmadC #performance #predict #simulation: Fast STA prediction-based gate-level timing simulation (TBA, MJC), pp. 1–6.
DATE-2014-ConosMDP #coordination #energy #power management #using: Provably minimal energy using coordinated DVS and power gating (NAC, SM, FD, MP), pp. 1–6.
DATE-2014-GholipourCSC #modelling #scalability: Highly accurate SPICE-compatible modeling for single- and double-gate GNRFETs with studies on technology scaling (MG, YYC, AS, DC), pp. 1–6.
DATE-2014-KondoKSWTNWAMKUKN #design #embedded #evaluation #fine-grained: Design and evaluation of fine-grained power-gating for embedded microprocessors (MK, HK, RS, MW, JT, MN, WW, HA, KM, MK, KU, TK, HN), pp. 1–6.
STOC-2014-Williams #algorithm #bound #linear: New algorithms and lower bounds for circuits with linear threshold gates (RW), pp. 194–202.
ICALP-v1-2014-LuWZ #fibonacci: FPTAS for Weighted Fibonacci Gates and Its Applications (PL, MW, CZ), pp. 787–799.
CGO-2014-DingEO #architecture #compilation #congruence: Single Assignment Compiler, Single Assignment Architecture: Future Gated Single Assignment Form*; Static Single Assignment with Congruence Classes (SD, JE, SÖ), p. 196.
HPCA-2014-BalasubramanianS #comprehension #execution #physics #reliability: Understanding the impact of gate-level physical reliability effects on whole program execution (RB, KS), pp. 60–71.
HPCA-2014-ChenZWP #named #performance: MP3: Minimizing performance penalty for power-gating of Clos network-on-chip (LC, LZ, RW, TMP), pp. 296–307.
DAC-2013-ChakrabortyLAP #physics: A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique (RC, CL, DA, JP), p. 10.
DAC-2013-Flynn #power management: Power gating applied to MP-SoCs for standby-mode power management (DF), p. 5.
DATE-2013-GaillardonABMSLM: Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs (PEG, LGA, SB, MDM, DS, YL, GDM), pp. 625–630.
DATE-2013-JoshiLBBG #estimation #performance #statistics: A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits (SJ, AL, MB, EB, SG), pp. 1056–1057.
DATE-2013-KahngKP #power management #reduction: Active-mode leakage reduction with data-retained power gating (ABK, SK, BP), pp. 1209–1214.
DATE-2013-LivramentoGGJ #performance: Fast and efficient lagrangian relaxation-based discrete gate sizing (VSL, CG, JLG, MOJ), pp. 1855–1860.
DATE-2013-MiryalaMCMP #configuration management #logic: A verilog-a model for reconfigurable logic gates based on graphene pn-junctions (SM, MM, AC, EM, MP), pp. 877–880.
DATE-2013-MishchenkoEBBMN #abstraction #named #revisited: GLA: gate-level abstraction revisited (AM, NE, RKB, JB, HM, PKN), pp. 1399–1404.
DATE-2013-TuHC: Co-synthesis of data paths and clock control paths for minimum-period clock gating (WPT, SHH, CHC), pp. 1831–1836.
DATE-2013-WangXZWYWNW #using: Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories (XW, JX, WZ, XW, YY, ZW, MN, ZW), pp. 1221–1224.
ICML-c2-2013-AlainO: Gated Autoencoders with Tied Input Weights (AD, OS), pp. 154–162.
ICML-c2-2013-SohnZLL #learning: Learning and Selecting Features Jointly with Point-wise Gated Boltzmann Machines (KS, GZ, CL, HL), pp. 217–225.
CASE-2012-ParkPC #automation #design #injection: Design automation of valve gate locations and open timing for injection molding of an automotive instrument panel (CHP, BGP, DHC), pp. 843–845.
DAC-2012-BobbaMLM #physics #synthesis: Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors (SB, MDM, YL, GDM), pp. 42–47.
DAC-2012-ChangB #simulation: Improving gate-level simulation accuracy when unknowns exist (KHC, CB), pp. 936–940.
DAC-2012-ChangJC #configuration management #optimisation #using: Timing ECO optimization using metal-configurable gate-array spare cells (HYC, IHRJ, YWC), pp. 802–807.
DAC-2012-SasanianWM #quantum #using: Realizing reversible circuits using a new class of quantum gates (ZS, RW, DMM), pp. 36–41.
DAC-2012-TovinakereSD #clustering #estimation #logic: A semiempirical model for wakeup time estimation in power-gated logic clusters (VDT, OS, SD), pp. 48–55.
DATE-2012-JeongKKRS #memory management #named #power management: MAPG: Memory access power gating (KJ, ABK, SK, TSR, RDS), pp. 1054–1059.
DATE-2012-PellegriniSCFHJAAB #evaluation: CrashTest’ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions (AP, RS, LC, XF, SKSH, JJ, SVA, TMA, VB), pp. 1106–1109.
DATE-2012-TangZBM #analysis #correlation #modelling #statistics: Transistor-level gate model based statistical timing analysis considering correlations (QT, AZ, MB, NvdM), pp. 917–922.
DATE-2012-WangRR #energy #runtime: Run-time power-gating in caches of GPUs for leakage energy savings (YW, SR, NR), pp. 300–303.
STOC-2012-GalHKPV #bound: Tight bounds on computing error-correcting codes by bounded-depth circuits with arbitrary gates (AG, KAH, MK, PP, EV), pp. 479–494.
DAC-2011-CevreroRSBIL #library #logic #power management #standard: Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library (AC, FR, MS, SB, PI, YL), pp. 1014–1019.
DAC-2011-FuketaIYTNSS #logic: A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates (HF, SI, TY, MT, MN, HS, TS), pp. 984–989.
DAC-2011-HenrySN #embedded #power management: A case for NEMS-based functional-unit power gating of low-power embedded microprocessors (MBH, MS, LN), pp. 872–877.
DAC-2011-LinH #satisfiability #using: Using SAT-based Craig interpolation to enlarge clock gating functions (THL, CY(H), pp. 621–626.
DAC-2011-XuLY #design #power management: Decoupling for power gating: sources of power noise and design strategies (TX, PL, BY), pp. 1002–1007.
DAC-2011-ZukoskiYM #logic: Universal logic modules based on double-gate carbon nanotube transistors (AZ, XY, KM), pp. 884–889.
DATE-2011-ChandraA: Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdown (VC, RCA), pp. 1172–1175.
DATE-2011-HsuL #optimisation: Clock gating optimization with delay-matching (SJH, RBL), pp. 643–648.
DATE-2011-KimCSY #modelling #parallel #performance #simulation #using: Temporal parallel simulation: A fast gate-level HDL simulation using higher level models (DK, MJC, KS, SY), pp. 1584–1589.
DATE-2011-KimCY #distributed #predict #simulation: A new distributed event-driven gate-level HDL simulation by accurate prediction (DK, MJC, SY), pp. 547–550.
DATE-2011-MistryAFH #power management: Sub-clock power-gating technique for minimising leakage power during active mode (JNM, BMAH, DF, SH), pp. 106–111.
DATE-2011-SterponeCMWF #configuration management #power management: A new reconfigurable clock-gating technique for low power SRAM-based FPGAs (LS, LC, DM, SW, FF), pp. 752–757.
DATE-2011-YangSSL #reduction #testing: A clock-gating based capture power droop reduction methodology for at-speed scan testing (BY, AS, SS, CL), pp. 197–203.
ICSE-2011-Chen #game studies #named #testing: GATE: game-based testing environment (NC), pp. 1078–1081.
HPCA-2011-MadanBBA #manycore #power management: A case for guarded power gating for multi-core processors (NM, AB, PB, MA), pp. 291–300.
DAC-2010-DadgourHSB #analysis #design #energy #logic #using: Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS (HFD, MMH, CS, KB), pp. 893–896.
DAC-2010-GuptaKKS #benchmark #heuristic #metric #named: Eyecharts: constructive benchmarking of gate sizing heuristics (PG, ABK, AK, PS), pp. 597–602.
DAC-2010-ObergHITSK #analysis #data flow: Theoretical analysis of gate level information flow tracking (JO, WH, AI, MT, TS, RK), pp. 244–247.
DAC-2010-SeomunSS #implementation #power management #synthesis: Synthesis and implementation of active mode power gating circuits (JS, IS, YS), pp. 487–492.
DAC-2010-TangZBM #analysis #simulation #statistics: RDE-based transistor-level gate simulation for statistical static timing analysis (QT, AZ, MB, NvdM), pp. 787–792.
DAC-2010-WeiMP #hardware #security: Gate-level characterization: foundations and hardware security applications (SW, SM, MP), pp. 222–227.
DATE-2010-ChenLTL #design #power management #standard: Power gating design for standard-cell-like structured ASICs (SYC, RBL, HHT, KWL), pp. 514–519.
DATE-2010-HenryN #power management: From transistors to MEMS: Throughput-aware power gating in CMOS circuits (MBH, LN), pp. 130–135.
DATE-2010-SrinivasJ #clustering #graph #performance: Clock gating approaches by IOEX graphs and cluster efficiency plots (JS, SJ), pp. 638–641.
DATE-2010-YangAFK #design #power management #reliability: Scan based methodology for reliable state retention power gating designs (SY, BMAH, DF, SSK), pp. 69–74.
CSCW-2010-KeeganG #social #social media: Egalitarians at the gate: one-sided gatekeeping practices in social media (BK, DG), pp. 131–134.
DAC-2009-ArbelER: Resurrecting infeasible clock-gating functions (EA, CE, OR), pp. 160–165.
DAC-2009-BawiecN #logic #synthesis: Boolean logic function synthesis for generalised threshold gate circuits (MAB, MN), pp. 83–86.
DAC-2009-ChatterjeeDB #simulation: Event-driven gate-level simulation with GP-GPUs (DC, AD, VB), pp. 557–562.
DAC-2009-FujitaKG #debugging: Debugging from high level down to gate level (MF, YK, AMG), pp. 627–630.
DAC-2009-LeeK #manycore #optimisation #throughput #using: Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating (JL, NSK), pp. 47–50.
DAC-2009-PotkonjakNNM #detection #hardware #using: Hardware Trojan horse detection using gate-level characterization (MP, AN, MN, TM), pp. 688–693.
DAC-2009-ShengXM #algorithm #fault #multi #optimisation #search-based #standard: Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm (WS, LX, ZM), pp. 502–507.
DAC-2009-WangCSC #graph #power management #synthesis #using: Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications (RW, NCC, BS, CKC), pp. 166–171.
DATE-2009-0002CWCXY #optimisation: Gate replacement techniques for simultaneous leakage and aging optimization (YW, XC, WW, YC, YX, HY), pp. 328–333.
DATE-2009-BolzaniCMMP #concurrent #design #industrial #power management: Enabling concurrent clock and power gating in an industrial design flow (LMVB, AC, AM, EM, MP), pp. 334–339.
DATE-2009-ChakrabortyGRP #analysis #optimisation: Analysis and optimization of NBTI induced clock skew in gated clock trees (AC, GG, AR, DZP), pp. 296–299.
DATE-2009-ChatterjeeDB #named #simulation: GCS: High-performance gate-level simulation with GPGPUs (DC, AD, VB), pp. 1332–1337.
DATE-2009-Held #design #scalability: Gate sizing for large cell-based designs (SH), pp. 827–832.
DATE-2009-JamaaMM #library #logic #multi #novel #synthesis: Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis (MHBJ, KM, GDM), pp. 622–627.
DATE-2009-KhursheedAH #design #fault #multi #reduction: Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing (SSK, BMAH, PH), pp. 1349–1354.
DATE-2009-LadharMB #fault #performance: Efficient and accurate method for intra-gate defect diagnoses in nanometer technology and volume data (AL, MM, LB), pp. 988–993.
ASPLOS-2009-TiwariWMMCS #data flow: Complete information flow tracking from the gates up (MT, HMGW, BM, SM, FTC, TS), pp. 109–120.
DAC-2008-ChangHHLWL: Type-matching clock tree for zero skew clock gating (CMC, SHH, YKH, JZL, HPW, YSL), pp. 714–719.
DAC-2008-FeldmannA #approach #modelling #physics #towards: Towards a more physical approach to gate modeling for timing, noise, and power (PF, SA), pp. 453–455.
DAC-2008-FraerKM #paradigm #synthesis: A new paradigm for synthesis and propagation of clock gating conditions (RF, GK, MKM), pp. 658–663.
DAC-2008-Hurst #automation #logic #synthesis: Automatic synthesis of clock gating logic with controlled netlist perturbation (APH), pp. 654–657.
DAC-2008-JiangM #power management #reduction #scheduling: Power gating scheduling for power/ground noise reduction (HJ, MMS), pp. 980–985.
DAC-2008-JiangS #algorithm #scalability: Circuit-wise buffer insertion and gate sizing algorithm with scalability (ZJ, WS), pp. 708–713.
DAC-2008-KellerTK #challenge #modelling: Challenges in gate level modeling for delay and SI at 65nm and below (IK, KHT, VK), pp. 468–473.
DAC-2008-PaikS #multi #optimisation #standard: Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements (SP, YS), pp. 600–605.
DAC-2008-RajaVBG #analysis #modelling #performance: Transistor level gate modeling for accurate and fast timing, noise, and power analysis (SR, FV, MRB, JG), pp. 456–461.
DATE-2008-FrenkilCU #analysis #design #physics #power management: Power Gating for Ultra-low Leakage: Physics, Design, and Analysis (JF, KC, KU).
DATE-2008-KulikowskiVWT: Power Balanced Gates Insensitive to Routing Capacitance Mismatch (KJK, VV, ZW, AT), pp. 1280–1285.
DATE-2008-LeinweberB #clustering #composition #fine-grained #reduction: Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction (LL, SB), pp. 373–378.
DATE-2008-MucciVMGDGKSCC #adaptation #array #configuration management #implementation #parallel #pipes and filters: Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array (CM, LV, IM, DG, AD, SG, JK, AS, LC, FC), pp. 1444–1449.
DATE-2008-SathanurPBMMP #algorithm #framework #scalability: A Scalable Algorithmic Framework for Row-Based Power-Gating (AVS, AP, LB, AM, EM, MP), pp. 379–384.
DATE-2008-ZhangZYZSPZCMSIC #multi #network: Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network (WZ, YZ, WY, LZ, RS, HP, ZZ, LCE, RM, TS, NI, CKC), pp. 537–540.
ICALP-C-2008-KolesnikovS: Improved Garbled Circuit: Free XOR Gates and Applications (VK, TS), pp. 486–498.
KDD-2008-CuiDSAJ #learning: Learning methods for lung tumor markerless gating in image-guided radiotherapy (YC, JGD, GCS, BMA, SBJ), pp. 902–910.
CAV-2008-EisnerNY #composition #design #functional #power management #reasoning #verification: Functional Verification of Power Gated Designs by Compositional Reasoning (CE, AN, KY), pp. 433–445.
DAC-2007-AksoyCFM #metric #optimisation #using: Optimization of Area in Digital FIR Filters using Gate-Level Metrics (LA, EACdC, PFF, JCM), pp. 420–423.
DAC-2007-HuKH #design: Gate Sizing For Cell Library-Based Designs (SH, MK, JH), pp. 847–852.
DAC-2007-LiuONG #configuration management #design #logic #novel: Novel CNTFET-based Reconfigurable Logic Gate Design (JL, IO, DN, FG), pp. 276–277.
DAC-2007-SinghalBSLNC #analysis #modelling #simulation: Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation (RS, AB, ARS, FL, SRN, YC), pp. 823–828.
DATE-2007-BaneresCK: Layout-aware gate duplication and buffer insertion (DB, JC, MK), pp. 1367–1372.
STOC-2007-Shpilka #multi: Interpolation of depth-3 arithmetic circuits with two multiplication gates (AS), pp. 284–293.
ICML-2007-LiaoLC #classification #semistructured data: Quadratically gated mixture of experts for incomplete data classification (XL, HL, LC), pp. 553–560.
DAC-2006-AnanthanR #physics #process: A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS (HA, KR), pp. 413–418.
DAC-2006-ChengDCW #algorithm #generative #performance #power management #reduction: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction (LC, LD, DC, MDFW), pp. 117–120.
DAC-2006-ChiouCCY #power management: Timing driven power gating (DSC, SHC, SCC, CY), pp. 121–124.
DAC-2006-DadgourJB #architecture #novel #power management: A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates (HFD, RVJ, KB), pp. 977–982.
DAC-2006-DavoodiS #optimisation #variability: Variability driven gate sizing for binning yield optimization (AD, AS), pp. 959–964.
DAC-2006-KimSKE #design #physics #power management #standard: Physical design methodology of power gating circuits for standard-cell-based design (HOK, YS, HK, IE), pp. 109–112.
DAC-2006-SwahnH: Gate sizing: finFETs vs 32nm bulk MOSFETs (BS, SH), pp. 528–531.
DATE-2006-AmelifardFP #using: Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment (BA, FF, MP), pp. 995–1000.
DATE-2006-BanerjeeRMB #fine-grained #logic #power management #synthesis #using: Low power synthesis of dynamic logic circuits using fine-grained clock gating (NB, KR, HMM, SB), pp. 862–867.
DATE-2006-Maurer #simulation #symmetry #using: Using conjugate symmetries to enhance gate-level simulations (PMM), pp. 638–643.
DATE-2006-MohantyVK #optimisation: Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits (SPM, RV, EK), pp. 1191–1196.
DATE-2006-SridharanC #modelling #multi #using: Modeling multiple input switching of CMOS gates in DSM technology using HDMR (JS, TC), pp. 626–631.
CIAA-2006-YangXSP #hybrid #quantum #synthesis: Universality of Hybrid Quantum Gates and Synthesis Without Ancilla Qudits (GY, FX, XS, MAP), pp. 279–280.
ICPR-v1-2006-DawoodBLJS #multi: Transforming Static CT in Gated PET/CT Studies to Multiple Respiratory Phases (MD, FB, NL, XJ, KPS), pp. 1026–1029.
DAC-2005-BhuniaBCMR #approach #novel #power management #reduction #synthesis #using: A novel synthesis approach for active leakage power reduction using dynamic supply gating (SB, NB, QC, HMM, KR), pp. 479–484.
DAC-2005-GaoH #multi #reduction: Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages (FG, JPH), pp. 31–36.
DAC-2005-LuoYYB #design #network #power management #using: Low power network processor design using clock gating (YL, JY, JY, LNB), pp. 712–715.
DAC-2005-SinghNLS #geometry #programming #robust: Robust gate sizing by geometric programming (JS, VN, ZQL, SSS), pp. 315–320.
DAC-2005-SrivastavaSASBD #correlation #estimation #parametricity #performance #power management: Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance (AS, SS, KA, DS, DB, SWD), pp. 535–540.
DAC-2005-TennakoonS #modelling #performance: Efficient and accurate gate sizing with piecewise convex delay models (HT, CS), pp. 807–812.
DAC-2005-YuanQ #reduction: Enhanced leakage reduction Technique by gate replacement (LY, GQ), pp. 47–50.
DATE-2005-AgarwalCB #optimisation #statistics #using: Statistical Timing Based Optimization using Gate Sizing (AA, KC, DB), pp. 400–405.
DATE-2005-CarterOS #concurrent #fault #modelling #testing: Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown (JRC, SO, DJS), pp. 300–305.
DATE-2005-KumarLTW #multi #probability #process #statistics: A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching (YSK, JL, CT, JMW), pp. 770–775.
DATE-2005-MullerTAL #design #multi #power management #top-down: Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit (PM, AT, SMA, YL), pp. 258–263.
DATE-2005-NeiroukhS #statistics #using: Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques (ON, XS), pp. 294–299.
DATE-2005-YangHSP #logic #multi #quantum #synthesis #using: Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory (GY, WNNH, XS, MAP), pp. 434–435.
STOC-2005-KouckyPT #bound: Bounded-depth circuits: separating wires from gates (MK, PP, DT), pp. 257–265.
ICALP-2005-ChattopadhyayH #bound #composition #symmetry: Lower Bounds for Circuits with Few Modular and Symmetric Gates (AC, KAH), pp. 994–1005.
SAC-2005-AdaikkalavanC #approach #named #security #web: SmartGate: a smart push-pull approach to support role-based security in web gateways (RA, SC), pp. 1727–1731.
HPCA-2005-JacobsonBHBZEEGLST #performance: Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors (HMJ, PB, ZH, AB, VVZ, RJE, LE, JG, DL, BS, JMT), pp. 238–242.
DAC-2004-AgarwalDB #multi #statistics: Statistical gate delay model considering multiple input switching (AA, FD, DB), pp. 658–663.
DAC-2004-GuptaKSS #effectiveness #runtime: Selective gate-length biasing for cost-effective runtime leakage control (PG, ABK, PS, DS), pp. 327–330.
DAC-2004-KanjLAR: Noise characterization of static CMOS gates (RK, TL, BA, ER), pp. 888–893.
DAC-2004-SrivastavaSB04a #power management #using: Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment (AS, DS, DB), pp. 783–787.
DAC-2004-TaylorS #array #energy #performance: Enabling energy efficiency in via-patterned gate array devices (RRT, HS), pp. 874–878.
DATE-v1-2004-BabighianBM #algorithm #scalability: A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks (PB, LB, EM), pp. 500–505.
DATE-v1-2004-BabighianBM04a #distributed: Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating (PB, LB, EM), pp. 720–723.
DATE-v2-2004-BernardiniPM: A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology (SB, JMP, PM), pp. 1404–1405.
DATE-v2-2004-Krupnova #experience #industrial #multi: Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience (HK), pp. 1236–1243.
DATE-v2-2004-RosselloS: A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk (JLR, JS), pp. 954–961.
ITiCSE-2004-Waraich #education #logic #using: Using narrative as a motivating device to teach binary arithmetic and logic gates (AW), pp. 97–101.
SAS-2004-HymansU #data flow #dependence #graph #static analysis: Static Analysis of Gated Data Dependence Graphs (CH, EU), pp. 197–211.
CGO-2004-CanalGS: Software-Controlled Operand-Gating (RC, AG, JES), pp. 125–136.
HPDC-2004-ChenRA #data type #distributed #middleware #named: GATES: A Grid-Based Middleware for Processing Distributed Data Streams (LC, KR, GA), pp. 192–201.
DAC-2003-BecerBAPOZH #reduction: Post-route gate sizing for crosstalk noise reduction (MRB, DB, IA, RP, CO, VZ, INH), pp. 954–957.
DAC-2003-BullockM: An arbitrary twoqubit computation In 23 elementary gates or less (SSB, ILM), pp. 324–329.
DAC-2003-DescampsBGIP #design #network #using: Design of a 17-million gate network processor using a design factory (GED, SB, SG, SI, AP), pp. 844–849.
DAC-2003-DonnoIBM #optimisation: Clock-tree power optimization based on RTL clock-gating (MD, AI, LB, EM), pp. 622–627.
DAC-2003-LeeKBS #analysis: Analysis and minimization techniques for total leakage considering gate oxide leakage (DL, WK, DB, DS), pp. 175–180.
DATE-2003-DingM #logic #modelling: Modeling Noise Transfer Characteristic of Dynamic Logic Gates (LD, PM), pp. 11114–11117.
HPCA-2003-LiBCVR #reduction: Deterministic Clock Gating for Microprocessor Power Reduction (HL, SB, YC, TNV, KR), pp. 113–122.
DAC-2002-AgarwalLR #named #power management: DRG-cache: a data retention gated-ground cache for low power (AA, HL, KR), pp. 473–478.
DAC-2002-AnisMEA #automation #clustering #performance #power management #reduction #using: Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique (MA, MM, MIE, SA), pp. 480–485.
DAC-2002-Berthet #design #industrial #mobile #multi: Going mobile: the next horizon for multi-million gate designs in the semi-conductor industry (CB), pp. 375–378.
DAC-2002-ChangC #implementation #self #verification: Self-referential verification of gate-level implementations of arithmetic circuits (YTC, KTC), pp. 311–316.
DAC-2002-MurugavelR #estimation #modelling #petri net: Petri net modeling of gate and interconnect delays for power estimation (AKM, NR), pp. 455–460.
DATE-2002-BayraktarogluO #fault: Gate Level Fault Diagnosis in Scan-Based BIST (IB, AO), pp. 376–381.
DATE-2002-BerkelaarE #effectiveness #performance: Efficient and Effective Redundancy Removal for Million-Gate Circuits (MRCMB, KvE), p. 1088.
DATE-2002-PronathGA #design #fault #float: A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits (MP, HEG, KA), pp. 78–83.
DATE-2002-Sheehan #library: Library Compatible Ceff for Gate-Level Timing (BNS), pp. 826–830.
FLOPS-2002-BandaDMS #tutorial: To the Gates of HAL: A HAL Tutorial (MJGdlB, BD, KM, PJS), pp. 47–66.
CIAA-2002-BrzozowskiG #algebra #simulation: Simulation of Gate Circuits in the Algebra of Transients (JAB, MG), pp. 57–66.
DAC-2001-ChenGB: A New Gate Delay Model for Simultaneous Switching and Its Applications (LCC, SKG, MAB), pp. 289–294.
DAC-2001-Ciriani #logic #using: Logic Minimization using Exclusive OR Gates (VC), pp. 115–120.
DAC-2001-LiebmannLHG #design #logic: Enabling Alternating Phase Shifted Mask Designs for a Full Logic Gate Level: Design Rules and Design Rule Checking (LL, JL, FLH, IG), pp. 79–84.
STOC-2001-RazS #bound #matrix: Lower bounds for matrix product, in bounded depth circuits with arbitrary gates (RR, AS), pp. 409–418.
DAC-2000-CongH #array #incremental #programmable: Depth optimal incremental mapping for field programmable gate arrays (JC, HH), pp. 290–293.
DAC-2000-NouraniCP: Synthesis-for-testability of controller-datapath pairs that use gated clocks (MN, JC, CAP), pp. 613–618.
DAC-2000-ZhouW #composition #power management: Optimal low power X OR gate decomposition (HZ, DFW), pp. 104–107.
DATE-2000-JacobsB #statistics #using: Gate Sizing Using a Statistical Delay Model (ETAFJ, MRCMB), pp. 283–290.
STOC-2000-DamMMS #fault tolerance #quantum #self #set: Self-testing of universal and fault-tolerant sets of quantum gates (WvD, FM, MM, MS), pp. 688–696.
DAC-1999-AlpertDQ: Buffer Insertion with Accurate Gate and Interconnect Delay Computation (CJA, AD, STQ), pp. 479–484.
DAC-1999-BertaccoDQ #simulation: Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits (VB, MD, SQ), pp. 391–396.
DAC-1999-HashimotoOT #design #power management #reduction: A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design (MH, HO, KT), pp. 446–451.
DAC-1999-JiangJC #optimisation #performance: Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation (IHRJ, JYJ, YWC), pp. 90–95.
DAC-1999-NotbauerANR #design #embedded #multi #verification: Verification and Management of a Multimillion-Gate Embedded Core Design (JN, TWA, GN, SR), pp. 425–428.
DAC-1999-YehCCJ #design: Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications (CWY, MCC, SCC, WBJ), pp. 68–71.
DATE-1999-BeniniMMMPS #power management: Glitch Power Minimization by Gate Freezing (LB, GDM, AM, EM, MP, RS), pp. 163–167.
DAC-1998-SalekLP #design: A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement Together (AHS, JL, MP), pp. 128–134.
DATE-1998-KassabCAK #analysis #constraints: Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis (MK, EC, SA, THK), pp. 796–802.
DATE-1998-LuSJ: Technology Mapping for Minimizing Gate and Routing Area (AL, GS, FMJ), pp. 664–669.
DATE-1998-OhP: Gated Clock Routing Minimizing the Switched Capacitance (JO, MP), pp. 692–697.
DATE-1998-RudnickVECPR #generative #performance #testing #using: Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques (EMR, RV, AE, FC, PP, MSR), pp. 570–576.
DAC-1997-DartuP #worst-case: Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling (FD, LTP), pp. 46–51.
EDTC-1997-BeniniMMPS #logic #network #optimisation #synthesis: Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks (LB, GDM, EM, MP, RS), pp. 514–520.
DAC-1996-BinhISH #algorithm #clustering #design #hardware #pipes and filters: A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts (NNB, MI, AS, NH), pp. 527–532.
DAC-1996-ChandramouliS #modelling #proximity: Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time (VC, KAS), pp. 617–622.
DAC-1996-ChenS #algorithm #power management: An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing (DSC, MS), pp. 783–788.
DAC-1996-CongH #composition #design: Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design (JC, YYH), pp. 726–729.
DAC-1996-CoudertHM #algorithm #case study #comparative: New Algorithms for Gate Sizing: A Comparative Study (OC, RWH, SM), pp. 734–739.
DAC-1996-KudvaGJN #multi #network #synthesis: Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes (PK, GG, HMJ, SMN), pp. 77–82.
DAC-1996-XiD #design #power management: Useful-Skew Clock Routing With Gate Sizing for Low Power Design (JGX, WWMD), pp. 383–388.
DAC-1995-MenezesPP #optimisation: Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization (NM, SP, LTP), pp. 690–695.
PLDI-1995-TuP #performance: Efficient Building and Placing of Gating Functions (PT, DAP), pp. 47–55.
ICML-1995-MaassW #learning #performance: Efficient Learning with Virtual Threshold Gates (WM, MKW), pp. 378–386.
DAC-1994-DartuMQP #performance: A Gate-Delay Model for high-Speed CMOS Circuits (FD, NM, JQ, LTP), pp. 576–580.
DAC-1994-KondratyevKLVY #implementation #independence: Basic Gate Implementation of Speed-Independent Circuits (AK, MK, BL, PV, AY), pp. 56–62.
DAC-1994-PrasadAB #design #incremental #synthesis: A System for Incremental Synthesis to Gate-Level and Reoptimization Following RTL Design Changes (SCP, PA, PWB), pp. 441–446.
EDAC-1994-DongenR #array #design: Advanced Analog Circuit Design on a Digital Sea-of-Gates Array (RvD, VR), pp. 70–74.
EDAC-1994-KunzmannB #fault: Gate-Delay Fault Test with Conventional Scan-Design (AK, FB), pp. 524–528.
EDAC-1994-WuM #2d #array #performance #programmable: An Efficient Router for 2-D Field Programmable Gate Arrays (YLW, MMS), pp. 412–416.
EDAC-1994-XueDJ #analysis #fault #float #probability: Probability Analysis for CMOS Floating Gate Faults (HX, CD, JAGJ), pp. 443–448.
STOC-1994-Grolmusz #trade-off: A weight-size trade-off for circuits with MOD m gates (VG), pp. 68–74.
STOC-1994-KrauseP #on the #power of: On the computational power of depth 2 circuits with threshold and modulo gates (MK, PP), pp. 48–57.
DAC-1993-ChanSZ #array #on the #predict #programmable: On Routability Prediction for Field-Programmable Gate Arrays (PKC, MDFS, JYZ), pp. 326–330.
DAC-1993-DamianiYM #logic #optimisation: Optimization of Combinational Logic Circuits Based on Compatible Gates (MD, JCYY, GDM), pp. 631–636.
DAC-1993-JoneF #identification #optimisation: Timing Optimization By Gate Resizing And Critical Path Identification (WBJ, CLF), pp. 135–140.
DAC-1993-KawarabayashiSS #verification: A Verification Technique for Gated Clock (MK, NVS, ALSV), pp. 123–127.
DAC-1993-MurgaiBS #array #programmable #synthesis: Sequential Synthesis for Table Look Up Programmable Gate Arrays (RM, RKB, ALSV), pp. 224–229.
DAC-1992-BoseA #concurrent #fault #logic #memory management #message passing #multi #simulation: Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing Multicomputers (SB, PA), pp. 332–335.
DAC-1992-Malik #multi #network #optimisation #using: Optimization of Primitive Gate Networks Using Multiple Output Two-Level Minimization (AAM), pp. 449–453.
DAC-1992-OkudaO #algorithm #generative #layout #performance: An Efficient Routing Algorithm for SOG Cell Generation on a Dense Gate-Isolated Layout Style (RO, SO), pp. 676–681.
DAC-1992-SawkarT #array #programmable: Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays (PS, DET), pp. 368–373.
STOC-1992-Beigel: When Do Extra Majority Gates Help? Polylog(n) Majority Gates Are Equivalent to One (RB), pp. 450–454.
WSA-1992-GiannottiL #abstract interpretation #specification #using: Using Abstract Interpretation for Gate splitting in LOTOS Specifications (FG, DL), pp. 194–204.
DAC-1991-ErcolaniM #array #programmable: Technology Mapping for Electrically Programmable Gate Arrays (SE, GDM), pp. 234–239.
DAC-1991-Hill #array #design #programmable: A CAD System for the Design of Field Programmable Gate Arrays (DDH), pp. 187–192.
DAC-1991-JainB #hardware #simulation: Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators (AJ, REB), pp. 219–222.
DAC-1991-Karplus #array #named #programmable: Xmap: A Technology Mapper for Table-Lookup Field-Programmable Gate Arrays (KK), pp. 240–243.
DAC-1991-Karplus91a #array #named #programmable: Amap: A Technology Mapper for Selector-Based Field-Programmable Gate Arrays (KK), pp. 244–247.
ML-1991-OliveiraS #concept #learning #network: Learning Concepts by Synthesizing Minimal Threshold Gate Networks (ALO, ALSV), pp. 193–197.
DAC-1990-FrancisRC #array #named #programmable: Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays (RJF, JR, KC), pp. 613–619.
DAC-1990-MatsumotoWUSHM #generative #layout: Datapath Generator Based on Gate-Level Symbolic Layout (NM, YW, KU, YS, HH, SM), pp. 388–393.
DAC-1990-MurgaiNSBS #array #logic #programmable #synthesis: Logic Synthesis for Programmable Gate Arrays (RM, YN, NVS, RKB, ALSV), pp. 620–625.
DAC-1990-SinghC #layout #matrix #order: A Transistor Reordering Technique for Gate Matrix Layout (US, CYRC), pp. 462–467.
STOC-1990-Szegedy #bound #communication #complexity #symmetry: Functions with Bounded Symmetric Communication Complexity and Circuits with mod m Gates (MS), pp. 278–286.
DAC-1989-AdamsS #generative #layout: Template Style Considerations for Sea-of-Gates Layout Generation (GDA, CHS), pp. 31–36.
DAC-1989-IgusaBS: ORCA a Sea-of-Gates Place and Route System (MI, MB, ALSV), pp. 122–127.
DAC-1989-IrwinO #2d #comparison #layout #matrix #tool support: A Comparison of Four Two-dimensional Gate Matrix Layout Tools (MJI, RMO), pp. 698–701.
DAC-1989-Leung #behaviour #modelling: Behavioral Modeling of Transmission Gates in VHDL (SSL), pp. 746–749.
DAC-1989-LinDY #2d #layout #matrix #synthesis: Gate Matrix Layout Synthesis with Two-Dimensional Folding (IL, DHCD, SHCY), pp. 37–42.
DAC-1988-Boehner #automation #logic #named: LOGEX — an Automatic Logic Extractor Form Transistor to Gate Level for CMOS Technology (MB), pp. 517–522.
DAC-1988-ChakravertiC #algorithm #array #metaprogramming: Routing Algorithm for Gate Array Macro Cells (AC, MJC), pp. 658–662.
DAC-1988-ChangCS #performance: An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits (FCC, CFC, PS), pp. 282–287.
DAC-1988-TsayKH #algorithm #named #performance: Proud: A Fast Sea-of-Gates Placement Algorithm (RST, ESK, CPH), pp. 318–323.
DAC-1987-ChangCH #approach #automation #generative #layout #matrix #using: Automated Layout Generation Using Gate Matrix Approach (YCC, SCC, LHH), pp. 552–558.
DAC-1987-RajsumanMJ #fault #modelling #on the: On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates (RR, YKM, APJ), pp. 244–250.
DAC-1986-FreemanKLN #automation #layout #matrix #modelling: Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning (RDF, SMK, CGLH, MLN), pp. 418–424.
DAC-1986-SaitoSYK #array #logic #rule-based #synthesis: A rule-based logic circuit synthesis system for CMOS gate arrays (TS, HS, MY, NK), pp. 594–600.
DAC-1986-ShinshaKSKI #identification #incremental #logic #synthesis: Incremental logic synthesis through gate logic structure identification (TS, TK, YS, JK, KI), pp. 391–397.
ICALP-1986-BrzozowskiS #analysis #network #simulation #summary: Correspondence between Ternary Simulation and Binary Race Analysis in Gate Networks (Extended Summary) (JAB, CJHS), pp. 69–78.
DAC-1985-DwyerMBG #array #automation #design #integration: The integration of an advanced gate array router into a fully automated design system (RD, SM, EB, DG), pp. 770–772.
DAC-1985-IachponiVBI #architecture #array #design: A hierarchical gate array architecture and design methodology (MI, DV, SB, AI), pp. 439–442.
DAC-1985-NodaYFKKF #algorithm #array #automation #layout: Automatic layout algorithms for function blocks of CMOS gate arrays (SN, HY, EF, HK, HK, TF), pp. 46–52.
DAC-1985-OgiharaSM #automation #generative #named #parametricity #testing: PATEGE: an automatic DC parametric test generation system for series gated ECL circuits (TO, SS, SM), pp. 212–218.
DAC-1985-SpiraH #array #hardware #layout: Hardware acceleration of gate array layout (PMS, CH), pp. 359–366.
DAC-1985-SteinwegAPN #array #compilation: Silicon compilation of gate array bases (RLS, SJA, KP, SN), pp. 435–438.
DAC-1984-Blanks #array #using: Initial placement of gate arrays using least-squares methods (JPB), pp. 670–671.
DAC-1984-EtiembleADB #algorithm #evaluation: Micro-computer oriented algorithms for delay evaluation of MOS gates (DE, VA, NHD, JCB), pp. 358–364.
DAC-1984-Hinchliffe #array #automation #design #physics: Commercial gate array physical design automation packages (FHI), pp. 386–387.
DAC-1984-ReddyAJ #detection #fault #logic: A gate level model for CMOS combinational logic circuits with application to fault detection (SMR, VDA, SKJ), pp. 504–509.
DAC-1984-TienTCCE #array #automation #layout #named: GALA — an automatic layout system for high density CMOS gate arrays (BNT, BST, JC, KSKC, SCE), pp. 657–662.
DAC-1984-WieclawskiP #compilation #layout #network #optimisation: Optimization of negative gate networks realized in weinberger-LIKF layout in a boolean level silicon compiler (AW, MAP), pp. 703–704.
DAC-1983-GamalS #array #statistics: A new statistical model for gate array routing (AEG, ZAS), pp. 671–674.
DAC-1983-GriersonCRHKKMMN #array #collaboration #design #development: The UK5000 — successful collaborative development of an integrated design system for a 5000 gate CMOS array with built-in test (JRG, BC, DR, REH, HK, JCK, JAM, JMM, CON), pp. 629–636.
DAC-1983-KirkCSBT #array: Placement of irregular circuit elements on non-uniform gate arrays (HK, PDC, JAS, JDB, GLT), pp. 637–643.
DAC-1983-KozakBG #array #design #simulation: Design aids for the simulation of bipolar gate arrays (PK, AKB, AG), pp. 286–292.
DAC-1983-Krohn #array: An over-cell gate array channel router (HEK), pp. 665–670.
DAC-1983-NewtonY #array #optimisation: Optimisation of global routing for the UK5000 gate array by iteration (CON, PAY), pp. 651–657.
DAC-1983-PrazicB #array #automation #using: Automatic routing of double layer gate arrays using a moving cursor (BDP, MAB), pp. 644–650.
DAC-1983-Robinson #array #automation #layout: Automatic layout for gate arrays with one layer of metal (PR0), pp. 658–664.
DAC-1982-GrayBR #array #compilation #design #using: Designing gate arrays using a silicon compiler (JPG, IB, PSR), pp. 377–383.
DAC-1982-KangKL #adaptation #cpu #design #evolution #layout #logic #matrix #random: Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design (SMK, RHK, HFSL), pp. 170–174.
DAC-1982-LuhukayK #layout #synthesis: A layout synthesis system for NMOS gate-cells (JFPL, WJK), pp. 307–314.
DAC-1982-McDermott #modelling: Transmission gate modeling in an existing three-value simulator (RMM), pp. 678–681.
DAC-1982-ToddHPBGAB #array #layout #multi: CGALA-a multi technology Gate Array Layout system (LFT, JMH, SVP, JLB, DJG, RJA, AKB), pp. 792–801.
DAC-1981-TanakaMNOTK #array #design #logic: An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2 (CT, SM, SN, TO, MT, KK), pp. 59–65.
DAC-1981-TanakaMTYOTKT #array #design #layout: An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3 (CT, SM, HT, TY, KO, MT, RK, MT), pp. 812–819.
DAC-1980-LuebbertU: Gate assignment and pack placement: Two approaches compared (FL, MU), pp. 472–482.
DAC-1979-Bening #logic #physics #simulation: Developments in computer simulation of gate level physical logic (LB), pp. 561–567.
DAC-1979-Wilcox #functional #logic #simulation: Digital logic simulation at the gate and functional level (PSW), pp. 242–248.
DAC-1978-NishiokaKYSO #approach: An approach to gate assignment and module placement for printed wiring boards (IN, TK, SY, IS, HO), pp. 60–69.
DAC-1977-SchulerC #fault #performance #simulation: An efficient method of fault simulation for digital circuits modeled from boolean gates and memories (DMS, RKC), pp. 230–238.
DAC-1976-Case #analysis #fault #logic: Analysis of actual fault mechanisms in CMOS logic gates (GRC), pp. 265–270.
DAC-1976-DobesB #automation #design #geometry #recognition: The automatic recognition of silicon gate transistor geometries: An LSI design aid program (ID, RB), pp. 327–335.
DAC-1974-Vaughn #array #functional #testing: Functional testing of LSI gate arrays (GDV), pp. 258–265.
DAC-1973-SzygendaL #functional #logic #simulation: Integrated techniques for functional and gate-level digital logic simulation (SAS, AAL), pp. 159–172.
DAC-1972-MahS: Techniques of gate assignment (LM, LS), pp. 63–71.
DAC-1972-Schmidt #composition #network: Gate for gate modular replacement of combinational switching networks (DCS), pp. 331–340.