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Travelled to:
1 × USA
Collaborated with:
T.Todman W.Luk
Talks about:
reconfigur (1) monitor (1) circuit (1) tempor (1) runtim (1) design (1) verif (1)

Person: Stephan Stilkerich

DBLP DBLP: Stilkerich:Stephan

Contributed to:

DAC 20152015

Wrote 1 papers:

DAC-2015-TodmanSL #configuration management #design #monitoring #runtime #verification
In-circuit temporal monitors for runtime verification of reconfigurable designs (TT, SS, WL), p. 6.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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