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Travelled to:
3 × USA
Collaborated with:
T.Kozawa Y.Ogawa C.Miura H.Terai A.Tsukizoe J.Sakemi T.Itoh Y.Miki Y.Sato R.Toyoshima Y.Shiraishi K.Yuyama K.Chiba M.Hayase K.Kishida N.Yamada Y.Ohno
Talks about:
placement (3) algorithm (3) lsis (2) high (2) interconnect (1) masterslic (1) constraint (1) mainfram (1) pattern (1) densiti (1)

Person: Tatsuki Ishii

DBLP DBLP: Ishii:Tatsuki

Contributed to:

DAC 19911991
DAC 19861986
DAC 19831983
DAC 19811981

Wrote 4 papers:

DAC-1991-OgawaIMIST #constraints #design
Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design (YO, TI, YM, TI, YS, RT), pp. 253–258.
DAC-1986-OgawaISTKYC #algorithm #optimisation #performance
Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs (YO, TI, YS, HT, TK, KY, KC), pp. 404–410.
DAC-1983-KozawaTIHMOKYO #algorithm #automation
Automatic placement algorithms for high packing density V L S I (TK, HT, TI, MH, CM, YO, KK, NY, YO), pp. 175–181.
DAC-1981-KozawaTSMI #algorithm #concurrent
A concurrent pattern operation algorithm for VLSI mask data (TK, AT, JS, CM, TI), pp. 563–570.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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