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Travelled to:
1 × France
Collaborated with:
A.M.Zarkesh M.Andrews
Talks about:
design (1) power (1) model (1) time (1) asic (1)

Person: Wolfgang Roethig

DBLP DBLP: Roethig:Wolfgang

Contributed to:

DATE 19981998

Wrote 1 papers:

DATE-1998-RoethigZA #design #modelling
Power and Timing Modeling for ASIC Designs (WR, AMZ, MA), pp. 969–970.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.