Stem asic$ (all stems)

59 papers:

DATE-2015-NowosielskiGBVB #design #fault tolerance #named

FLINT: layout-oriented FPGA-based methodology for fault tolerant ASIC design (RN, LG, SB, GPV, HB), pp. 297–300.

DATE-2014-LiuW #configuration management #design #embedded #logic #obfuscation

Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks (BL, BW), pp. 1–6.

DAC-2013-GaillardonMABSLM #towards #using

Towards structured ASICs using polarity-tunable Si nanowire transistors (PEG, MDM, LGA, SB, DS, YL, GDM), p. 4.

DATE-2013-GaillardonABMSLM

Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs (PEG, LGA, SB, MDM, DS, YL, GDM), pp. 625–630.

DATE-2012-GuoSHGHNS #implementation

ASIC implementations of five SHA-3 finalists (XG, MS, SH, DG, MBH, LN, PS), pp. 1006–1011.

DATE-2012-TsaiLL #analysis #configuration management #design

Design and analysis of via-configurable routing fabrics for structured ASICs (HPT, RBL, LCL), pp. 1479–1482.

DATE-2012-YangCJTZ #multi #protocol #smarttech

A multi-parameter bio-electric ASIC sensor with integrated 2-wire data transmission protocol for wearable healthcare system (GY, JC, FJ, HT, LRZ), pp. 443–448.

DATE-2010-ChenLTL #design #power management #standard

Power gating design for standard-cell-like structured ASICs (SYC, RBL, HHT, KWL), pp. 514–519.

DATE-2010-LiSBNO #analysis #implementation

Power Variance Analysis breaks a masked ASIC implementation of AES (YL, KS, LB, DN, KO), pp. 1059–1064.

DAC-2009-ChakrabortyKP #framework #named #open source #quality

RegPlace: a high quality open-source placement framework for structured ASICs (AC, AK, DZP), pp. 442–447.

DAC-2009-Chesters #development #lifecycle #verification

Role of the verification team throughout the ASIC development life cycle (EC), pp. 216–219.

CIKM-2009-WuBTJDS #algebra #comparison #named

ASIC: algebra-based structural index comparison (YW, SB, TT, SJ, DD, MS), pp. 2111–2112.

DAC-2008-LiBNPC #approach #how #implementation #power management #set

How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach (ML, BB, DN, LVdP, FC), pp. 345–346.

DATE-2007-BaguenaLBDOBH #development #flexibility #generative

Development of on board, highly flexible, Galileo signal generator ASIC (LB, EL, AB, JMD, CO, PB, VH), pp. 679–683.

DATE-2007-PapadonikolakisPK #implementation #performance

Efficient high-performance ASIC implementation of JPEG-LS encoder (MEP, VP, AK), pp. 159–164.

DATE-2006-MallikSBZ #design #optimisation #power management

Smart bit-width allocation for low power optimization in a systemc based ASIC design environment (AM, DS, PB, HZ), pp. 618–623.

DATE-DF-2006-HuttonYSBCCP #synthesis #verification

A methodology for FPGA to structured-ASIC synthesis and verification (MH, RY, JS, GB, SC, KKC, HKP), pp. 64–69.

DAC-2005-ChangD #perspective

Explaining the gap between ASIC and custom power: a custom perspective (AC, WJD), pp. 281–284.

DAC-2005-ChinneryK #perspective

Closing the power gap between ASIC and custom: an ASIC perspective (DGC, KK), pp. 275–280.

DAC-2005-WilsonGHMLBTC #framework #question

Structured/platform ASIC apprentices: which platform will survive your board room? (RW, JG, CH, KM, SL, IB, RT, RC), pp. 887–888.

DAC-2005-WongKP #flexibility #multi

Flexible ASIC: shared masking for multiple media processors (JLW, FK, MP), pp. 909–914.

DAC-2004-DeoZBCGLRRS #question #what

What happened to ASIC?: Go (recon)figure? (ND, BZ, IB, JC, BG, PL, CBR, CR, RS), p. 185.

DATE-DF-2004-DaddaMO #design

The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512) (LD, MM, JO), pp. 70–75.

DATE-DF-2004-RenWBLLD #design

A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications (BR, AW, JB, KL, WL, WWMD), pp. 280–285.

DATE-v1-2004-TiriV #design #implementation #logic

A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation (KT, IV), pp. 246–251.

DAC-2003-BittlestoneHSA #architecture #library

Architecting ASIC libraries and flows in nanometer era (CB, AMH, VS, NVA), pp. 776–781.

DAC-2003-LackeyZK #design

Designing mega-ASICs in nanogate technologies (DEL, PSZ, JK), pp. 770–775.

DAC-2003-PuriSCKPSSK #performance

Pushing ASIC performance in a power envelope (RP, LS, JMC, DSK, DZP, DS, AS, SHK), pp. 788–793.

DAC-2002-SantariniJMEKRRY #question

Whither (or wither?) ASIC handoff? (MS, SJ, MM, TE, SK, KNR, TR, KY), pp. 317–318.

DAC-2001-ChinneryNK

Achieving 550Mhz in an ASIC Methodology (DGC, BN, KK), pp. 420–425.

DAC-2001-RichPS #design #perspective

Reducing the Frequency Gap Between ASIC and Custom Designs: A Custom Perspective (SER, MJP, JS), pp. 432–437.

DAC-2001-Zeijl #challenge

One-chip Bluetooth ASIC Challenges (PTMvZ), p. 262.

DAC-2000-ChinneyK #perspective

Closing the gap between ASIC and custom: an ASIC perspective (DGC, KK), pp. 637–642.

DAC-2000-DallyC #design

The role of custom design in ASIC Chips (WJD, AC), pp. 643–647.

DAC-1999-YimBK

A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs (JSY, SOB, CMK), pp. 766–771.

DATE-1999-CmarRSVB #design #fixpoint #refinement

A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement (RC, LR, PS, SV, IB), p. 271–?.

DAC-1998-EvansSVBDHHL #functional #scalability #verification

Functional Verification of Large ASICs (AE, AS, GV, TB, MD, GH, TH, YL), pp. 650–655.

DAC-1998-SchaumontVREB #design #programming

A Programming Environment for the Design of Complex High Speed ASICs (PS, SV, LR, ME, IB), pp. 315–320.

DATE-1998-HamiltonO #concurrent #fault #latency

Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs (SNH, AO), pp. 604–609.

DATE-1998-RabeJKNO #performance #trade-off

Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs (DR, GJ, LK, WN), pp. 356–361.

DATE-1998-RoethigZA #design #modelling

Power and Timing Modeling for ASIC Designs (WR, AMZ, MA), pp. 969–970.

SAC-1998-EconomakosPT #attribute grammar #multi #synthesis

Incorporating multi-pass attribute grammars for the high-level synthesis of ASICs (GE, GKP, PT), pp. 45–49.

LCTES-1998-Campbell #architecture #embedded

Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications (MC), p. 261.

EDTC-1997-GibsonA #concurrent #design #verification

Practical concurrent ASIC and system design and verification (IG, CA), pp. 532–536.

EDTC-1997-RiescoDMCSJ #multi #network #on the

On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC (JR, JCD, LAM, JLC, CS, EJM), pp. 218–222.

CAV-1997-Hughes #approach #verification

Formal Verification of Digital Systems, from ASICs to HW/SW Codesign — a Pragmatic Approach (RBH), pp. 3–6.

DAC-1996-SrivastavaP #approach #implementation #linear #optimisation #programmable

Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-based Approach (MBS, MP), pp. 343–348.

DAC-1995-BombanaCCHMZ #case study #synthesis

Design-Flow and Synthesis for ASICs: A Case Study (MB, PC, SC, RBH, GM, GZ), pp. 292–297.

DAC-1995-MartinK #behaviour #named #optimisation #power management

Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level (RSM, JPK), pp. 42–47.

DAC-1994-KellyPC #agile #prototype

Rapid Prototyping of ASIC Based Systems (PHK, KJP, PMC), pp. 460–465.

EDAC-1994-DonnaySGSKL #automation #design

A Methodology for Analog Design Automation in Mixed-Signal ASICs (SD, KS, GGEG, WMCS, WK, DL), pp. 530–534.

EDAC-1994-GreinerLWW #complexity #design #library

Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library (AG, LL, FW, LW), pp. 9–13.

EDAC-1994-MichelLSDC #dependence

Taking Advantage of ASICs to Improve Dependability with Very Low Overheads (TM, RL, GS, RD, PC), pp. 14–18.

DAC-1992-KarriO #fault tolerance #synthesis

Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs (RK, AO), pp. 662–665.

DAC-1989-Keutzer #architecture #design #generative #logic #synthesis

Three Competing Design Methodologies for ASIC’s: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation (KK), pp. 308–313.

DAC-1989-Muller-GlaserB #approach #design #specification #using

An Approach to Intelligent Assistance for the Specification of ASIC Design Using Objects and Rules (KDMG, JB), pp. 472–477.

DAC-1989-RumseyS #simulation

An ASIC Methodology for Mixed Analog-Digital Simulation (MR, JS), pp. 618–621.

DAC-1989-SaabR #approach #clustering

An Evolution-Based Approach to Partitioning ASIC Systems (YS, VBR), pp. 767–770.

DAC-1987-LeungS #concept #design #framework #hardware

A Conceptual Framework for Designing ASIC Hardware (SSL, MAS), pp. 592–595.