BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × Germany
Collaborated with:
F.Yang X.Zeng Y.Su
Talks about:
transistor (1) macromodel (1) nonlinear (1) piecewis (1) approach (1) circuit (1) reduct (1) linear (1) effici (1) order (1)

Person: Xiaoda Pan

DBLP DBLP: Pan:Xiaoda

Contributed to:

DATE 20102010

Wrote 1 papers:

DATE-2010-PanYZS #approach #megamodelling #order #performance #reduction
An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits (XP, FY, XZ, YS), pp. 1673–1676.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.