VHDL Synthesis Using Structured Modeling
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Joseph Lis, Daniel Gajski
VHDL Synthesis Using Structured Modeling
DAC, 1989.

DAC 1989
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@inproceedings{DAC-1989-LisG,
	author        = "Joseph Lis and Daniel Gajski",
	booktitle     = "{Proceedings of the 26th Design Automation Conference}",
	doi           = "10.1145/74382.74486",
	pages         = "606--609",
	publisher     = "{ACM Press}",
	title         = "{VHDL Synthesis Using Structured Modeling}",
	year          = 1989,
}

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