Stem vhdl$ (all stems)

83 papers:

DATE-2010-DietrichEH #analysis #statistics #using

Digital statistical analysis using VHDL (MD, UE, JH), pp. 1007–1010.

ITiCSE-2010-ShoufanLR #framework #synthesis #visualisation

A platform for visualizing digital circuit synthesis with VHDL (AS, ZL, GR), pp. 294–298.

ECMDA-FA-2008-WoodAHM #array

Array OL Descriptions of Repetitive Structures in VHDL (SW, DHA, WGJH, KDMM), pp. 137–152.

SAC-2008-GruianW #architecture #case study #embedded #java

VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture (FG, MW), pp. 1492–1497.

DATE-DF-2004-BaileyMBLA #design #verification

Improving Design and Verification Productivity with VHDL-200x (SB, EM, JB, JL, PJA), pp. 332–335.

DATE-DF-2004-HeckerCLBLO #development #library

VHDL-AMS Library Development for Pacemaker Applications (BH, MC, ML, EB, LL, JO), pp. 338–341.

DATE-v1-2004-ReNR #automation #generative

A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters (ADR, AN, MR), pp. 686–687.

DATE-v1-2004-WilsonRBKB #behaviour #modelling #performance

Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS (PRW, JNR, ADB, TJK, JB), pp. 742–743.

DATE-v2-2004-Fitzpatric

System Verilog for VHDL Users (TF), pp. 1334–1341.

DATE-2003-AholaWS #design

Bluetooth Transceiver Design with VHDL-AMS (RA, DW, MS), pp. 20268–20273.

DATE-2003-BombanaB #synthesis

SystemC-VHDL Co-Simulation and Synthesis in the HW Domain (MB, FB), pp. 20101–20105.

DAC-2002-MadesG #graph #modelling #using

Regularization of hierarchical VHDL-AMS models using bipartite graphs (JM, MG), pp. 548–551.

DATE-2002-Leveugle #automation #detection #fault

Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance (RL), pp. 837–841.

DATE-2002-WilsonRZBK #behaviour #fault #modelling #using

Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS (PRW, JNR, MZ, ADB, YK), p. 1133.

SAS-2002-Hymans #abstract interpretation #behaviour #safety

Checking Safety Properties of Behavioral VHDL Descriptions by Abstract Interpretation (CH), pp. 444–460.

DAC-2001-JaniszewskiHM #design #performance #reuse

VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers (IJ, BH, HM), pp. 573–578.

DATE-2001-RonaK #modelling #using

Modelling SoC devices for virtual test using VHDL (MR, GK), pp. 770–771.

DATE-2001-StuikysZDM #component

Two approaches for developing generic components in VHDL (VS, GZ, RD, GM), p. 800.

DATE-2000-FinF #fault #functional #generative #testing

A VHDL Error Simulator for Functional Test Generation (AF, FF), pp. 390–395.

DATE-2000-LungeanuS #distributed #parallel #simulation

Parallel and Distributed VHDL Simulation (DL, CJRS), pp. 658–662.

DATE-2000-PeraliasARH #design #pipes and filters #verification

A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters (EJP, AJA, AR, JLH), pp. 534–538.

DAC-1999-HansenNR #algorithm #approach #specification

An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications (CH, FN, WR), pp. 678–683.

DATE-1999-BarnaR #object-oriented #reuse

Object-Oriented Reuse Methodology for VHDL (CB, WR), p. 689–?.

DATE-1999-BreuerMBFLK #reasoning #semantics #using

Reasoning about VHDL and VHDL-AMS using Denotational Semantics (PTB, NMM, JPB, RBF, MMLP, CDK), pp. 346–352.

DATE-1999-DoboliV #architecture #behaviour #compilation #generative #synthesis

A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems (AD, RV), pp. 338–345.

DATE-1999-FerrandiFGS #functional #generative #specification

Symbolic Functional Vector Generation for VHDL Specifications (FF, FF, LG, DS), p. 442–?.

DATE-1999-MartinolleDCF #user interface

Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI (FM, CD, DC, MF), pp. 788–789.

DATE-1999-Sasaki #semantics #simulation #state machine

A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine (HS), p. 353–?.

DATE-1999-TabbaraSSFL #modelling #performance #using

Fast Hardware-Software Co-simulation Using VHDL Models (BT, MS, ALSV, EF, LL), p. 309–?.

DATE-1999-X #ada #c #java #question #specification

Java, VHDL-AMS, ADA or C for System Level Specifications?, p. 720.

AdaEurope-1999-LopezVV #ada #design #embedded #hardware #using

Hardware/Software Embedded System Specifiaction and Design Using Ada and VHDL (AL, MV, EV), pp. 356–370.

DATE-1998-CoppensAR #analysis #fault #modelling

VHDL Modelling and Analysis of Fault Secure Systems (JC, DAK, CR), pp. 148–152.

DATE-1998-Kazmierski

A Formal Description of VHDL-AMS Analogue Systems (TJK), pp. 916–920.

DATE-1998-MoserM #design #modelling #named

VHDL-AMS: The Missing Link in System Design — Experiments with Unified Modelling in Automotive Engineering (EM, NM), pp. 59–63.

DATE-1998-Mrva #object-oriented #reuse

Enhanced Reuse and Teamwork Capabilities for an Object-oriented Extension of VHDL (MM), pp. 250–256.

DATE-1998-Mutz #modelling

Register Transfer Level VHDL Models without Clocks (MM), pp. 153–158.

DATE-1998-Naroska #parallel #simulation

Parallel VHDL Simulation (EN), pp. 159–163.

DATE-1998-Nicoli #behaviour #semantics #set

Denotational Semantics of a Behavioral Subset of VHDL (FN), pp. 975–976.

DATE-1998-OlcozAIP

VHDL Teamwork, Organization Units and Workspace Management (SO, LA, II, OP), pp. 297–302.

DATE-1998-Putzke-RomingRN #flexibility #message passing

A Flexible Message Passing Mechanism for Objective VHDL (WPR, MR, WN), pp. 242–249.

DATE-1998-ReetzSK #hardware #specification #verification

Formal Specification in VHDL for Hardware Verification (RR, KS, TK), pp. 257–263.

DATE-1998-TanFY #design

The Design of an Asynchronous VHDL Synthesizer (SYT, SBF, WFY), pp. 44–51.

DATE-1998-WahlV #performance #validation

A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor (MGW, HV), pp. 937–938.

SIGAda-1998-MillsP #ada #analysis #co-evolution #design #hardware #migration

Hardware/Software Co-Design: VHDL and Ada 95 Code Migration and Integrated Analysis (MM, GP), pp. 18–27.

DAC-1997-BauerE #approach #hardware

Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach (MB, WE), pp. 774–779.

EDTC-1997-WalkerG #simulation

VHDL extensions for complex transmission line simulation (PW, SG), pp. 368–372.

DAC-1996-LeeHCF #design #modelling #synthesis #using

Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL (MTCL, YCH, BC, MF), pp. 585–590.

DAC-1996-Smith #c

VHDL & Verilog Compared & Contrasted — Plus Modeled Example Written in VHDL, Verilog and C (DJS), pp. 771–776.

DAC-1996-WunderLM #concept #layout #modelling #named #simulation

VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems (BW, GL, KDMG), pp. 119–124.

DAC-1995-GiumaleK #modelling

Information Models of VHDL (CAG, HJK), pp. 678–683.

DAC-1995-StollonP #behaviour #complexity #metric #modelling

Measures of Syntactic Complexity for Modeling Behavioral VHDL (NSS, JDP), pp. 684–689.

DAC-1995-WalkerG #algorithm #distributed #execution #parallel #simulation

Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors (PAW, SG), pp. 144–150.

DAC-1995-ZepterGM #data flow #design #generative #graph #using

Digital Receiver Design Using VHDL Generation from Data Flow Graphs (PZ, TG, HM), pp. 228–233.

DAC-1994-LeviaMR #analysis #design

Lessons in Language Design: Cost/Benefit analysis of VHDL Features (OL, SM, JR), pp. 447–453.

EDAC-1994-BreuerFK #semantics

Clean formal semantics for VHDL (PTB, LSF, CDK), pp. 641–647.

EDAC-1994-FrosslK #simulation

A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation (JF, TK), pp. 343–348.

PLILP-1994-SaenzHRW #memory management #specification

Shared Memory System for Babel: a VHDL Specification (FS, WH, JJR, SW), pp. 461–462.

DAC-1993-Tatarnikov

The State of VHDL in Russia (YT), pp. 709–711.

CAV-1993-CourcoubetisDJ #verification

Verification of timing Properties of VHDL (CC, WD, BJ), pp. 225–236.

DAC-1992-StollD #constraints #synthesis

High-Level Synthesis from VHDL with Exact Timing Constraints (AS, PD), pp. 188–193.

DAC-1992-VishakantaiahAA #automation

Automatic Test Knowledge Extraction from VHDL (ATKET) (PV, JAA, MSA), pp. 273–278.

DAC-1991-PitchumaniMR #fault #simulation

A System for Fault Diagnosis and Simulation of VHDL Descriptions (VP, PM, NR), pp. 144–150.

ICLP-1991-Reintjes #design #set #tool support

A Set of Tools for VHDL Design (PBR), pp. 549–562.

DAC-1990-ArmstrongCSK #validation

The VHDL Validation Suite (JA, CC, SS, CK), pp. 2–7.

DAC-1990-ChungK #design #object-oriented

An Object-Oriented VHDL Design Environment (MJC, SK), pp. 431–436.

DAC-1990-WardA #behaviour #fault #simulation

Behavioral Fault Simulation in VHDL (PCW, JRA), pp. 587–593.

DAC-1989-JordanW #composition #named

COMP: A VHDL Composition System (PRJ, RDW), pp. 750–753.

DAC-1989-Leung #behaviour #modelling

Behavioral Modeling of Transmission Gates in VHDL (SSL), pp. 746–749.

DAC-1989-LiawTL #named #verification

VVDS: A Verification/Diagnosis System for VHDL (HTL, KTT, CSL), pp. 435–440.

DAC-1989-LisG #modelling #synthesis #using

VHDL Synthesis Using Structured Modeling (JL, DG), pp. 606–609.

PLDI-1989-FarrowS #attribute grammar #compilation

A VHDL Compiler Based on Attribute Grammar Methodology (RF, AGS), pp. 120–130.

DAC-1988-AcostaAIR

The Role of VHDL in the MCC CAD System (RDA, MA, GI, BR), pp. 34–39.

DAC-1988-AugustinGHLS #design #using #verification

Verification of VHDL Designs Using VAL (LMA, BAG, YH, DCL, AGS), pp. 48–53.

DAC-1988-Coelho #named #standard

VHDL: A Call for Standards (DRC), pp. 40–47.

DAC-1988-KimTH #automation #hardware #using

Automatic Insertion of BIST Hardware Using VHDL (KK, JGT, DSH), pp. 9–15.

DAC-1987-Brei #metalanguage #named #representation

Needed: A Meta-Language for Evaluating the Expressiveness of EDIF, IGES, VHDL and Other Representation Mechanisms (MLB), p. 565.

DAC-1987-ChunCM #named

VISION: VHDL Induced Schematic Imaging on Net-Lists (RKC, KJC, LPM), pp. 436–442.

DAC-1987-Hines

Where VHDL Fits Within the CAD Environment (JH), pp. 491–494.

DAC-1987-Saunders #design

The IBM VHDL Design System (LFS), pp. 484–490.

DAC-1987-Shahdad #interface

An Interface between VHDL and EDIF (MS), pp. 472–478.

DAC-1986-Shahdad #bibliography

An overview of VHDL language and technology (MS), pp. 320–326.

DAC-1984-Dewey #hardware

The VHSIC hardware description language (VHDL) program (AD), pp. 556–557.

DAC-1983-Dewey #development #hardware

VHSIC hardware description (VHDL) development program (AD), pp. 625–628.