Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits
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David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller
Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits
DATE, 2008.

DATE 2008
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@inproceedings{DATE-2008-FeinsteinTM,
	author        = "David Y. Feinstein and Mitchell A. Thornton and D. Michael Miller",
	booktitle     = "{Proceedings of the 12th Conference on Design, Automation and Test in Europe}",
	doi           = "10.1109/DATE.2008.4484932",
	isbn          = "978-3-9810801-3-1",
	pages         = "1378--1381",
	publisher     = "{IEEE}",
	title         = "{Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits}",
	year          = 2008,
}

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