Proceedings of the 12th Conference on Design, Automation and Test in Europe
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Proceedings of the 12th Conference on Design, Automation and Test in Europe
DATE, 2008.

SYS
DBLP
Scholar
Full names Links ISxN
@proceedings{DATE-2008,
	address       = "Munich, Germany",
	isbn          = "978-3-9810801-3-1",
	publisher     = "{IEEE}",
	title         = "{Proceedings of the 12th Conference on Design, Automation and Test in Europe}",
	year          = 2008,
}

Contents (295 items)

DATE-2008-BeckerHEHSL #architecture #communication #design
Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems (JB, MH, RE, AH, WS, VL).
DATE-2008-BinkleyGGR #design
From Transistor to PLL — Analogue Design and EDA Methods (DB, HEG, GGEG, JSR).
DATE-2008-ElgertHOHB
DfM in the Analogue and Digital World (CE, VH, AO, TH, EB).
DATE-2008-ErnstJSBC #analysis #formal method #optimisation #performance
Formal Methods in System and MpSoC Performance Analysis and Optimisation (RE, MJ, HS, MB, SC).
DATE-2008-FrenkilCU #analysis #design #physics #power management
Power Gating for Ultra-low Leakage: Physics, Design, and Analysis (JF, KC, KU).
DATE-2008-GizopoulosRGNW #power management #testing
Power-Aware Testing and Test Strategies for Low Power Devices (DG, KR, PG, NN, XW).
DATE-2008-GizopoulosRMS #case study #fault
Soft Errors: System Effects, Protection Techniques and Case Studies (DG, KR, SM, PS).
DATE-2008-LeupersAVAV #architecture #design #multi
System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures (RL, GA, WV, TA, AV).
DATE-2008-MarculescuN #architecture #challenge #design #variability
Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level (DM, SRN).
DATE-2008-MostermanOSJKRCM #automation #embedded #functional #modelling
Automatically Realising Embedded Systems from High-Level Functional Models (PJM, DO, JS, AAJ, WK, VR, CGC, GM).
DATE-2008-VillarJGK #specification #using
Heterogeneous System-level Specification Using SystemC (EV, AJ, CG, TK).
DATE-2008-Micheli #design
Designing Micro/Nano Systems for a Safer and Healthier Tomorrow (GDM), p. 1.
DATE-2008-Vernay #challenge #embedded #research
Perspective on Embedded Systems: Challenges, Solutions and Research Priorities (DV), p. 2.
DATE-2008-HwangAG #approximate #estimation #performance #transaction
Cycle-approximate Retargetable Performance Estimation at the Transaction Level (YH, SA, DG), pp. 3–8.
DATE-2008-CornetMM #development #modelling #performance #transaction
A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip (JC, FM, LMC), pp. 9–14.
DATE-2008-BombieriDF #automation #design #generative
Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation (NB, ND, FF), pp. 15–20.
DATE-2008-Fuss #safety
Tailored Solutions for Safety-Installations in the Loetschberg Tunnel — A Project with Importance for the Trans-European Rail Traffic (WF), pp. 21–25.
DATE-2008-FreuerJGN #constraints #design #higher-order #on the #verification
On the Verification of High-Order Constraint Compliance in IC Design (JBF, GJ, JG, WN), pp. 26–31.
DATE-2008-KruijtzerWKSEMHAPV #industrial #integration #standard
Industrial IP Integration Flows based on IP-XACT Standards (WK, PvdW, EAdK, JS, WE, AM, SH, CA, SdP, EV), pp. 32–37.
DATE-2008-VogtW #configuration management #set
A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment (TV, NW), pp. 38–43.
DATE-2008-CopeCL #configuration management #gpu #logic #memory management #using
Using Reconfigurable Logic to Optimise GPU Memory Accesses (BC, PYKC, WL), pp. 44–49.
DATE-2008-PaulssonHB #integration #metric #power management
Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs (KP, MH, JB), pp. 50–55.
DATE-2008-NeumannSBN #architecture #design #embedded #flexibility
Design flow for embedded FPGAs based on a flexible architecture template (BN, TvS, HB, TGN), pp. 56–61.
DATE-2008-TcheghoMS
Optimal High-Resolution Spectral Analyzer (AT, HM, SS), pp. 62–67.
DATE-2008-StratigopoulosTM #estimation #parametricity
A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation (HGDS, JT, SM), pp. 68–73.
DATE-2008-ZjajoG #analysis #fault #multi
Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters (AZ, JPdG), pp. 74–79.
DATE-2008-AsianVR #implementation #network
Practical Implementation of a Network Analyzer for Analog BIST Applications (MJBA, DV, AR), pp. 80–85.
DATE-2008-Katoen #analysis #design #embedded #evaluation #modelling #roadmap
Quantitative Evaluation in Embedded System Design: Trends in Modeling and Analysis Techniques (JPK), pp. 86–87.
DATE-2008-CosteGHHTZ #architecture #design #embedded #evaluation #parallel #thread #validation
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures (NC, HG, HH, RH, YT, MZ), pp. 88–89.
DATE-2008-ClothH #design #embedded #evaluation #mobile #predict
Quantitative Evaluation in Embedded System Design: Predicting Battery Lifetime in Mobile Devices (LC, BRH), pp. 90–91.
DATE-2008-TanQ #framework #markov #power management #probability #using
A Framework of Stochastic Power Management Using Hidden Markov Model (YT, QQ), pp. 92–97.
DATE-2008-ZhouPB #analysis #generative #metric #modelling #using
Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement (YZ, SP, SB), pp. 98–103.
DATE-2008-BrunelliBMT #energy #performance
An Efficient Solar Energy Harvester for Wireless Sensor Nodes (DB, LB, CM, LT), pp. 104–109.
DATE-2008-MuraliMAGBBM #manycore #optimisation #platform #using
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization (SM, AM, DA, RG, SPB, LB, GDM), pp. 110–115.
DATE-2008-GhamarianGBS #analysis #data flow #graph #parametricity #throughput
Parametric Throughput Analysis of Synchronous Data Flow Graphs (AHG, MG, TB, SS), pp. 116–121.
DATE-2008-SchirnerD #modelling #scheduling #using
Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling (GS, RD), pp. 122–127.
DATE-2008-GruttnerONCF #modelling #refinement #synthesis
SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder (KG, FO, WN, FCB, AMF), pp. 128–133.
DATE-2008-VasilevskiPBAE #modelling
Modeling and Refining Heterogeneous Systems With SystemC-AMS: Application to WSN (MV, FP, NB, HA, KE), pp. 134–139.
DATE-2008-MassierGS #design
Sizing Rules for Bipolar Analog Circuit Design (TM, HEG, US), pp. 140–145.
DATE-2008-KazmierskiZA #approximate #mobile #modelling #performance #using
Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density (TJK, DZ, BMAH), pp. 146–151.
DATE-2008-AliWWB #approach #behaviour #modelling #performance
A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits (SA, RW, PRW, ADB), pp. 152–157.
DATE-2008-GlassLRHT #analysis #network #optimisation #reliability
Symbolic Reliability Analysis and Optimization of ECU Networks (MG, ML, FR, CH, JT), pp. 158–163.
DATE-2008-LettninNRKRKSR #embedded #verification
Verification of Temporal Properties in Automotive Embedded Software (DL, PKN, JR, TK, WR, TK, VS, SR), pp. 164–169.
DATE-2008-StubeSHL #approach #design #novel
A Novel Approach for EMI Design of Power Electronics (BS, BS, EH, AL), pp. 170–175.
DATE-2008-AltCS #algorithm #architecture #detection #hardware #realtime
Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments (NA, CC, WS), pp. 176–181.
DATE-2008-SinanogluM #analysis #composition #reduction #testing
Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing (OS, EJM), pp. 182–187.
DATE-2008-LarssonLCEP #architecture #optimisation #scheduling
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns (AL, EL, KC, PE, ZP), pp. 188–193.
DATE-2008-BernardiR #novel #testing
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers (PB, MSR), pp. 194–199.
DATE-2008-VinkBW #analysis #architecture #performance
Performance Analysis of SoC Architectures Based on Latency-Rate Servers (JPV, KvB, PvdW), pp. 200–205.
DATE-2008-PandeyD #architecture #memory management #optimisation
Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs (SP, RD), pp. 206–211.
DATE-2008-HolzenspiesHKS #multi #runtime #streaming
Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC) (PKFH, JH, JK, GJMS), pp. 212–217.
DATE-2008-KimPH #architecture #multi
Architecture Exploration of NAND Flash-based Multimedia Card (SK, CP, SH), pp. 218–223.
DATE-2008-JungP #nondeterminism #power management
Resilient Dynamic Power Management under Uncertainty (HJ, MP), pp. 224–229.
DATE-2008-MoserTBB #complexity #robust
Robust and Low Complexity Rate Control for Solar Powered Sensors (CM, LT, DB, LB), pp. 230–235.
DATE-2008-LiuQW #energy #realtime
Energy Aware Dynamic Voltage and Frequency Selection for Real-Time Systems with Energy Harvesting (SL, QQ, QW), pp. 236–241.
DATE-2008-HongYBCEK #bias #runtime #scalability
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution (SH, SY, BB, KMC, SKE, TK), pp. 242–247.
DATE-2008-ChattopadhyayZ #debugging #online
Built-in Clock Skew System for On-line Debug and Repair (AC, ZZ), pp. 248–251.
DATE-2008-Rimolo-DonadioSGKR #analysis #metric #optimisation
Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects (RRD, CS, XG, YHK, MBR), pp. 252–255.
DATE-2008-KoN08a #automation #generative #on the #validation
On Automated Trigger Event Generation in Post-Silicon Validation (HFK, NN), pp. 256–259.
DATE-2008-BatcherW #embedded #scheduling
Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems (KWB, RAW), pp. 260–263.
DATE-2008-QuSN #configuration management #performance #runtime
Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking (YQ, JPS, JN), pp. 264–267.
DATE-2008-DongZ #integration #logic #standard #synthesis
Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration (MD, LZ), pp. 268–271.
DATE-2008-ChavesKSV
Merged Computation for Whirlpool Hashing (RC, GK, LS, SV), pp. 272–275.
DATE-2008-MeyerowitzSSL #multi #simulation
Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor (TM, ALSV, MS, DL), pp. 276–279.
DATE-2008-Garcia #automation #configuration management
Safe Automatic Flight Back and Landing of Aircraft Flight Reconfiguration Function (FRF) (JAHG), pp. 280–283.
DATE-2008-VenutoR #generative
PWM-Based Test Stimuli Generation for BIST of High Resolution ADCs (DDV, LR), pp. 284–287.
DATE-2008-ChantemDH #realtime #scheduling
Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs (TC, RPD, XSH), pp. 288–293.
DATE-2008-AvnitDSRP #approach #formal method #problem #protocol
A Formal Approach To The Protocol Converter Problem (KA, VD, AS, SR, SP), pp. 294–299.
DATE-2008-MoonenBBM #multi #streaming
Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip (AM, MB, RvdB, JLvM), pp. 300–305.
DATE-2008-HooverB #network
Synthesizing Synchronous Elastic Flow Networks (GH, FB), pp. 306–311.
DATE-2008-VytyazHMM #analysis #constraints #design #similarity
Periodic Steady-State Analysis Augmented with Design Equality Constraints (IV, PKH, UKM, KM), pp. 312–317.
DATE-2008-GouraryRUZMG #analysis #injection
Analysis of Oscillator Injection Locking by Harmonic Balance Method (MMG, SGR, SLU, MMZ, BJM, KKG), pp. 318–323.
DATE-2008-SteinhorstH #model checking #specification #using
Model Checking of Analog Systems using an Analog Specification Language (SS, LH), pp. 324–329.
DATE-2008-GailliardBSV #component #corba #protocol #semantics
Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components (GG, HB, MS, FV), pp. 330–335.
DATE-2008-SterponeATG #design #fault tolerance #on the #safety
On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications (LS, MAA, JNT, HGM), pp. 336–341.
DATE-2008-MelaniBMLDF #monitoring
Hot Wire Anemometric MEMS Sensor for Water Flow Monitoring (MM, LB, MDM, PL, FD, LF), pp. 342–347.
DATE-2008-NessL #design #fault tolerance #statistics
Guiding Circuit Level Fault-Tolerance Design with Statistical Methods (DCN, DJL), pp. 348–353.
DATE-2008-NagpalGK #approach #design #using
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements (CN, RG, SPK), pp. 354–359.
DATE-2008-RaoO #fault tolerance #parallel #towards
Towards fault tolerant parallel prefix adders in nanoelectronic systems (WR, AO), pp. 360–365.
DATE-2008-GhoshNR #adaptation #fault tolerance #novel #using
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking (SG, PN, KR), pp. 366–371.
DATE-2008-BeutelBDL #embedded #tutorial
Embedded Tutorial — Software for Wireless Networked Embedded Systems (JB, MB, AD, KL), p. 372.
DATE-2008-LeinweberB #clustering #composition #fine-grained #reduction
Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction (LL, SB), pp. 373–378.
DATE-2008-SathanurPBMMP #algorithm #framework #scalability
A Scalable Algorithmic Framework for Row-Based Power-Gating (AVS, AP, LB, AM, EM, MP), pp. 379–384.
DATE-2008-PakbazniaP #using
Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting (EP, MP), pp. 385–390.
DATE-2008-ForestFASSN #architecture #physics
Physical Architectures of Automotive Systems (TF, AF, GA, MS, ALSV, MDN), pp. 391–395.
DATE-2008-BombieriFP #communication #interface
A Mutation Model for the SystemC TLM 2.0 Communication Interfaces (NB, FF, GP), pp. 396–401.
DATE-2008-WuH #algorithm #design #performance #validation
Efficient Design Validation Based on Cultural Algorithms (WW, MSH), pp. 402–407.
DATE-2008-Marques-SilvaP #algorithm #satisfiability #using
Algorithms for Maximum Satisfiability using Unsatisfiable Cores (JMS, JP), pp. 408–413.
DATE-2008-TangX #debugging #transaction
In-band Cross-Trigger Event Transmission for Transaction-Based Debug (ST, QX), pp. 414–419.
DATE-2008-SilvaPS #analysis #performance #power management #representation
Efficient Representation and Analysis of Power Grids (JMSS, JRP, LMS), pp. 420–425.
DATE-2008-SrivastavaSB #multi
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate (NS, RS, KB), pp. 426–431.
DATE-2008-LiTM #analysis #grid #named #network #power management
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis (DL, SXDT, BM), pp. 432–437.
DATE-2008-HalakY #optimisation
Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods (BH, AY), pp. 438–443.
DATE-2008-LiBXNPC #architecture #detection #optimisation #parallel #programmable
Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures (ML, BB, WX, DN, LVdP, FC), pp. 444–449.
DATE-2008-KumarB
Vectorization of Reed Solomon Decoding and Mapping on the EVP (AK, KvB), pp. 450–455.
DATE-2008-MayAW #case study #design
A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder (MM, MA, NW), pp. 456–461.
DATE-2008-ChandraNK #architecture #power management #reduction #testing
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction (AC, FN, RK), pp. 462–467.
DATE-2008-ElmW #embedded
Scan Chain Organization for Embedded Diagnosis (ME, HJW), pp. 468–473.
DATE-2008-TenentesKK #testing
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores (VT, XK, EK), pp. 474–479.
DATE-2008-BrownTBP #automation #library #logic #testing
Automated Testability Enhancements for Logic Brick Libraries (JGB, BT, RDB, LTP), pp. 480–485.
DATE-2008-DavidLLN #approach #game studies #realtime #testing
A Game-Theoretic Approach to Real-Time System Testing (AD, KGL, SL, BN), pp. 486–491.
DATE-2008-RoxE #modelling
Modeling Event Stream Hierarchies with Hierarchical Event Models (JR, RE), pp. 492–497.
DATE-2008-GheorgheBNB #modelling #semantics #validation
Semantics for Model-Based Validation of Continuous/Discrete Systems (LG, FB, GN, HB), pp. 498–503.
DATE-2008-BrisolaraORLCW #code generation #uml #using
Using UML as Front-end for Heterogeneous Software Code Generation Strategies (LBdB, MFdSO, RMR, LCL, LC, FRW), pp. 504–509.
DATE-2008-Schat #clustering #fault #process
Fault Clustering in deep-submicron CMOS Processes (JS), pp. 511–514.
DATE-2008-DuanK #energy #performance
Energy Efficient and High Speed On-Chip Ternary Bus (CD, SPK), pp. 515–518.
DATE-2008-RedaelliSS #anti #configuration management #scheduling
Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems (FR, MDS, DS), pp. 519–522.
DATE-2008-PradhanV #performance #synthesis #using
Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches (AP, RV), pp. 523–526.
DATE-2008-Liu08a #correlation #performance #random #simulation
Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression (BL), pp. 527–532.
DATE-2008-GaidKSH #design #embedded #lifecycle
A methodology for improving software design lifecycle in embedded control systems (MEMBG, RK, YS, RH), pp. 533–536.
DATE-2008-ZhangZYZSPZCMSIC #multi #network
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network (WZ, YZ, WY, LZ, RS, HP, ZZ, LCE, RM, TS, NI, CKC), pp. 537–540.
DATE-2008-GlasKSMB #architecture #configuration management #platform
A System Architecture for Reconfigurable Trusted Platforms (BG, AK, OS, KDMG, JB), pp. 541–544.
DATE-2008-RoginKFDR #automation #design #generative #hardware
Automatic Generation of Complex Properties for Hardware Designs (FR, TK, GF, RD, SR), pp. 545–548.
DATE-2008-HeineckeDJMKSN #component #reliability
Software Components for Reliable Automotive Systems (HH, WD, BJ, AM, HK, ALSV, MDN), pp. 549–554.
DATE-2008-Hanselmann
Model-Based-Design Is Nice But.. (HH), p. 555.
DATE-2008-SamiiREP #distributed #estimation #realtime #simulation #worst-case
A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems (SS, SR, PE, ZP), pp. 556–561.
DATE-2008-Liu #analysis #probability #statistics
Signal Probability Based Statistical Timing Analysis (BL), pp. 562–567.
DATE-2008-AmelifardHFP #logic #multi #stack
A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect (BA, SH, HF, MP), pp. 568–573.
DATE-2008-GoelV #analysis #standard
Current source based standard cell model for accurate signal integrity and timing analysis (AG, SBKV), pp. 574–579.
DATE-2008-ZhangYWYJX #correlation #performance #process #statistics
An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation (WZ, WY, ZW, ZY, RJ, JX), pp. 580–585.
DATE-2008-VillenaS #algorithm #named #order #reduction #scalability
SPARE — a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction (JFV, LMS), pp. 586–591.
DATE-2008-ClineCBTS #modelling
Transistor-Specific Delay Modeling for SSTA (BC, KC, DB, AT, SS), pp. 592–597.
DATE-2008-LiNBPC #architecture #multi
Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications (ML, DN, BB, LVdP, FC), pp. 598–603.
DATE-2008-KoenigSB #algorithm #novel #recursion
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms (RK, TS, JB), pp. 604–609.
DATE-2008-BonnotLEGRG #approach #architecture #implementation #multi
Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA (PB, FL, GE, GG, OR, PG), pp. 610–615.
DATE-2008-SreedharSK #fault #modelling #on the #testing
On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits (AS, AS, SK), pp. 616–621.
DATE-2008-XiongZVH
Optimal Margin Computation for At-Speed Test (JX, VZ, CV, PAH), pp. 622–627.
DATE-2008-EngelkePSB #fault #industrial #simulation
Resistive Bridging Fault Simulation of Industrial Circuits (PE, IP, JS, BB), pp. 628–633.
DATE-2008-LinPBB #detection
Physically-Aware N-Detect Test Pattern Selection (YTL, OP, NKB, RDB), pp. 634–639.
DATE-2008-WiggersBS #communication #throughput
Computation of Buffer Capacities for Throughput Constrained and Data Dependent Inter-Task Communication (MW, MB, GJMS), pp. 640–645.
DATE-2008-KimSTDV #adaptation #constraints #online #refinement
Constraint Refinement for Online Verifiable Cross-Layer System Adaptation (MK, MOS, CLT, ND, NV), pp. 646–651.
DATE-2008-MalaniMQW #adaptation #multi #nondeterminism #realtime #scalability #scheduling
Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-time Applications with Non-deterministic Workload (PM, PM, QQ, QW), pp. 652–657.
DATE-2008-SchutzGBG #approach #embedded #research #tutorial
Embedded Tutorial — ARTEMIS and ENIAC Joint Undertakings: A New Approach to Conduct Research in Europe (ES, KG, DB, LG), p. 658.
DATE-2008-FrankWESN #analysis #architecture #design #evaluation #standard #tool support
Methods, Tools and Standards for the Analysis, Evaluation and Design of Modern Automotive Architectures (EF, RW, RE, ALSV, MDN), pp. 659–663.
DATE-2008-PlazaMB #constraints #generative #random #using
Random Stimulus Generation using Entropy and XOR Constraints (SP, ILM, VB), pp. 664–669.
DATE-2008-WagnerB #adaptation #design #manycore #named #verification
MCjammer: Adaptive Verification for Multi-core Designs (IW, VB), pp. 670–675.
DATE-2008-GerinGP #implementation #performance #simulation
Efficient Implementation of Native Software Simulation for MPSoC (PG, XG, FP), pp. 676–681.
DATE-2008-ChengH #invariant #mining #verification
Simulation-Directed Invariant Mining for Software Verification (XC, MSH), pp. 682–687.
DATE-2008-MomeniBG #comparison
Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation (MM, PBB, MG), pp. 688–693.
DATE-2008-LiCZ #novel
A Novel Technique for Improving Temperature Independency of Ring-ADC (SL, HC, FZ), pp. 694–697.
DATE-2008-BacinschiMKG #adaptation #bias
An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs (PBB, TM, KK, MG), pp. 698–703.
DATE-2008-WangKABT #approach #energy #modelling #optimisation #performance
Integrated approach to energy harvester mixed technology modelling and performance optimisation (LW, TJK, BMAH, SPB, RNT), pp. 704–709.
DATE-2008-EberleG #architecture #automation #communication #design #network #power management #scalability
A scalable low-power digital communication network architecture and an automated design path for controlling the analog/RF part of SDR transceivers (WE, MG), pp. 710–715.
DATE-2008-BougardSRNADP #array
A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio (BB, BDS, SR, DN, OA, SD, LVdP), pp. 716–721.
DATE-2008-NovoBLPC #energy #fixpoint #refinement
Scenario-Based Fixed-point Data Format Refinement to Enable Energy-scalable Software Defined Radios (DN, BB, AL, LVdP, FC), pp. 722–727.
DATE-2008-RavikumarHW #power management
Test Strategies for Low Power Devices (CPR, MH, XW), pp. 728–733.
DATE-2008-MulasPBCABAM #architecture #multi #policy #streaming
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures (FM, MP, MB, SC, AA, LB, DA, GDM), pp. 734–739.
DATE-2008-CertnerLPTAD #approach #parallel #performance #predict #source code
A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs (OC, ZL, PP, OT, FA, ND), pp. 740–745.
DATE-2008-HashemiG #algorithm #approximate #pipes and filters #synthesis
Exact and Approximate Task Assignment Algorithms for Pipelined Software Synthesis (MH, SG), pp. 746–751.
DATE-2008-BauerSKH #embedded #runtime #set
Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set (LB, MS, SK, JH), pp. 752–757.
DATE-2008-LinF #parallel #performance #source code
Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency (HL, YF), pp. 758–763.
DATE-2008-WuCSC #architecture #multi #set
Instruction Set Extension Exploration in Multiple-Issue Architecture (IWW, ZYC, JJJS, CPC), pp. 764–769.
DATE-2008-BonnyH #embedded #encoding
Instruction Re-encoding Facilitating Dense Embedded Code (TB, JH), pp. 770–775.
DATE-2008-VersenSSD #analysis #locality
Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM devices (MV, AS, JS, DD), pp. 776–779.
DATE-2008-RistauLF #design #framework
A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs (BR, TL, GF), pp. 780–783.
DATE-2008-HaidZLK #communication
Impact of Leakage Current on Data Retention of RF-powered Devices During Amplitude-Modulation-based Communication (JH, BZ, TL, TK), pp. 784–787.
DATE-2008-RadetzkiK #adaptation #modelling #simulation #transaction
Accuracy-Adaptive Simulation of Transaction Level Models (MR, RSK), pp. 788–791.
DATE-2008-WangZHZT #design #multi #reliability
Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor (JW, HZ, KH, GZ, YT), pp. 792–795.
DATE-2008-ChenL #architecture
Wire Sizing Alternative — An Uniform Dual-rail Routing Architecture (FWC, YYL), pp. 796–799.
DATE-2008-WangH #multi #synthesis
Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology (XW, LH), pp. 800–803.
DATE-2008-LewickiPTDJ #design #prototype
A Virtual Prototype for Bluetooth over Ultra Wide Band System Level Design (AL, JdPP, JT, ED, GJ), pp. 804–807.
DATE-2008-YuanHX #using
Re-Examining the Use of Network-on-Chip as Test Access Mechanism (FY, LH, QX), pp. 808–811.
DATE-2008-LaiHK #identification #multi #verification
Improving Constant-Coefficient Multiplier Verification by Partial Product Identification (CYL, CYH, KYK), pp. 813–818.
DATE-2008-NanshiS
Improved Visibility in One-to-Many Trace Concretization (KN, FS), pp. 819–824.
DATE-2008-AronsEOSS #low level #performance #simulation
Efficient Symbolic Simulation of Low Level Software (TA, EE, SO, JS, ES), pp. 825–830.
DATE-2008-GanaiG #smt #source code
Completeness in SMT-based BMC for Software Programs (MKG, AG), pp. 831–836.
DATE-2008-MeisterLT #algorithm #component #novel
Novel Pin Assignment Algorithms for Components with Very High Pin Counts (TM, JL, GT), pp. 837–842.
DATE-2008-BadelGIMVGL #design #difference #standard
A Generic Standard Cell Design Methodology for Differential Circuit Styles (SB, EG, OI, APM, PV, FKG, YL), pp. 843–848.
DATE-2008-ChakrabortySP #layout #optimisation
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices (AC, SXS, DZP), pp. 849–855.
DATE-2008-SingheeSR #correlation #kernel #performance #statistics
Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing (AS, SS, RAR), pp. 856–861.
DATE-2008-MorgadoRR #configuration management #multi #standard
A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications (AM, RdR, JMdlR), pp. 862–867.
DATE-2008-BingesserLHHMDV #metric
Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement (MB, TL, WH, JH, SM, RD, MV), pp. 868–872.
DATE-2008-BadarogluDLC #using
Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment (MB, GD, FL, OC), pp. 873–878.
DATE-2008-DAscoliBMFRPVFM #programmable
A Programmable and Low-EMI Integrated Half-Bridge Driver in BCD Technology (FD, LB, MM, LF, GR, EP, FV, MF, MDM), pp. 879–884.
DATE-2008-LiMM #concurrent #named #self #using
CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns (YL, SM, SM), pp. 885–890.
DATE-2008-ZhangHXL #fault #manycore #using
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology (LZ, YH, QX, XL), pp. 891–896.
DATE-2008-VemuJAPG #concurrent #detection #fault #logic #low cost
A low-cost concurrent error detection technique for processor control logic (RV, AJ, JAA, SP, RG), pp. 897–902.
DATE-2008-ChoudhuryM #approximate #concurrent #detection #fault #logic
Approximate logic circuits for low overhead, non-intrusive concurrent error detection (MRC, KM), pp. 903–908.
DATE-2008-ChatterjeeGHIKPS #logic #realtime #reliability
Logical Reliability of Interacting Real-Time Tasks (KC, AG, TAH, DTI, CMK, CP, ALSV), pp. 909–914.
DATE-2008-IzosimovPEP #constraints #embedded #fault tolerance #scheduling
Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints (VI, PP, PE, ZP), pp. 915–920.
DATE-2008-ElmqvistN #analysis #component #incremental #tool support
Tool Support for Incremental Failure Mode and Effects Analysis of Component-Based Systems (JE, SNT), pp. 921–927.
DATE-2008-TalpinOBG #composition #design
Compositional design of isochronous systems (JPT, JO, LB, PLG), pp. 928–933.
DATE-2008-BadstubnerV #design #metric
Quantitative Productivity Measurement in IC Design (FB, AV), pp. 934–935.
DATE-2008-HauslerPHHN #analysis #design
Qalitative and Quantitative Analysis of IC Designs (SH, FP, KH, AH, WN), pp. 935–936.
DATE-2008-LeppeltB #complexity
Determining the Technical Complexity of Integrated Circuits (PL, EB), p. 935.
DATE-2008-Young #design #metric
Capturing and Analyzing IC Design Productivity Metrics (JY), pp. 936–937.
DATE-2008-WeinbergerBB #design #modelling #petri net #process #verification #workflow
Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits (KW, SB, RB), pp. 937–938.
DATE-2008-Brand #design #manycore #optimisation
Optimization of Design Flows for Multi-Core x86 Microprocessors in 45 and 32nm Technologies under Productivity Considerations (HJB), pp. 938–939.
DATE-2008-Abraham #dependence #roadmap
Implications of Technology Trends on System Dependability (JAA), p. 940.
DATE-2008-Mitra #challenge #reliability #robust
Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges (SM), pp. 941–946.
DATE-2008-WapplerM
Software Protection Mechanisms for Dependable Systems (UW, MM), pp. 947–952.
DATE-2008-StrikGW #concurrent #design #process
Subsystem Exchange in a Concurrent Design Process Environment (MS, AG, PW), pp. 953–958.
DATE-2008-PenazziCDSSM #multi #safety
Cooperative Safety: a Combination of Multiple Technologies (RP, PC, MD, AS, MS, EM), pp. 959–961.
DATE-2008-MayerH #architecture #optimisation #performance
System Performance Optimization Methodology for Infineon’s 32-Bit Automotive Microcontroller Architecture (AM, FH), pp. 962–966.
DATE-2008-StefanoBBM #design #multi #pipes and filters #process
Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style (BS, DB, LB, EM), pp. 967–972.
DATE-2008-CalimeraBM #constraints #performance #power management
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints (AC, LB, EM), pp. 973–978.
DATE-2008-GargMK
A Single-supply True Voltage Level Shifter (RG, GM, SPK), pp. 979–984.
DATE-2008-CorderoK #using
Clock Distribution Scheme using Coplanar Transmission Lines (VHCC, SPK), pp. 985–990.
DATE-2008-MolnosHC #composition #embedded #multi
Compositional, dynamic cache management for embedded chip multiprocessors (AMM, MJMH, SDC), pp. 991–996.
DATE-2008-MassasP #comparison #manycore #memory management #policy
Comparison of memory write policies for NoC based Multicore Cache Coherent Systems (PGdM, FP), pp. 997–1002.
DATE-2008-OggVAYDB
Serialized Asynchronous Links for NoC (SO, EV, BMAH, AY, CD, LB), pp. 1003–1008.
DATE-2008-ZhangPM #design #guidelines #logic
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits (JZ, NP, SM), pp. 1009–1014.
DATE-2008-WilleLDG #logic #quantifier #synthesis
Quantified Synthesis of Reversible Logic (RW, HML, GWD, DG), pp. 1015–1020.
DATE-2008-AllecKS #adaptation #simulation
Adaptive Simulation for Single-Electron Devices (NA, RGK, LS), pp. 1021–1026.
DATE-2008-RinconPRZSAPM #energy #estimation #framework #network #platform
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks (FJR, MP, JR, QZ, MSE, DA, JP, GDM), pp. 1027–1032.
DATE-2008-MasrurDF #polynomial #testing
Improvements in Polynomial-Time Feasibility Testing for EDF (AM, SD, GF), pp. 1033–1038.
DATE-2008-TumeoBCCMPFS #multi #realtime
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications (AT, MB, LC, MC, MM, GP, FF, DS), pp. 1039–1044.
DATE-2008-DiederichsMSW
An application-based EDF scheduler for OSEK/VDX (CD, UM, FS, GW), pp. 1045–1050.
DATE-2008-FranchinoBF #protocol
Time Properties of the BuST Protocol under the NPA Budget Allocation Scheme (GF, GCB, TF), pp. 1051–1056.
DATE-2008-CongX #network
Simultaneous FU and Register Binding Based on Network Flow Method (JC, JX), pp. 1057–1062.
DATE-2008-WangSX #framework #synthesis
A Variation Aware High Level Synthesis Framework (FW, GS, YX), pp. 1063–1068.
DATE-2008-RoyKM #named
EPIC: Ending Piracy of Integrated Circuits (JAR, FK, ILM), pp. 1069–1074.
DATE-2008-ZezzaM #implementation
VLSI implementation of SISO arithmetic decoders for joint source channel coding (SZ, GM), pp. 1075–1078.
DATE-2008-FrechetteL #algorithm #detection #fault #self
Error Detection/Correction in DNA Algorithmic Self-Assembly (SF, FL), pp. 1079–1082.
DATE-2008-BaoAEP #energy #optimisation
Temperature-Aware Voltage Selection for Energy Optimization (MB, AA, PE, ZP), pp. 1083–1086.
DATE-2008-FangH #algorithm #approximate #performance #satisfiability
A Fast Approximation Algorithm for MIN-ONE SAT (LF, MSH), pp. 1087–1090.
DATE-2008-ZengC #analysis #polynomial #random
Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis (JKZ, CPC), pp. 1091–1094.
DATE-2008-LuMGB #algorithm #for free #performance
An efficient algorithm for free resources management on the FPGA (YL, TM, GG, KB), pp. 1095–1098.
DATE-2008-YoshidaF
Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits (HY, MF), pp. 1099–1102.
DATE-2008-BahukudumbiCK #scheduling
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs (SB, KC, RK), pp. 1103–1106.
DATE-2008-ScheerSB #complexity #reduction #standard
CARbridge, Reduction of System Complexity by Standardisation of the System-Basis-Chips for Automotive Applications (PS, ES, SB), pp. 1107–1110.
DATE-2008-IsrarH #design #embedded #reliability #specification
Specification and Design Considerations for Reliable Embedded Systems (AI, SAH), pp. 1111–1116.
DATE-2008-ElesIPP #embedded #fault tolerance #synthesis
Synthesis of Fault-Tolerant Embedded Systems (PE, VI, PP, ZP), pp. 1117–1122.
DATE-2008-Kopetz #reliability
Reliable Services in an Imperfect World (HK), p. 1123.
DATE-2008-WolfH #requirements #video
Video Processing Requirements on SoC Infrastructures (PvdW, TH), pp. 1124–1125.
DATE-2008-Pamunuwa #integration #memory management #scalability
Memory Technology for Extended Large-Scale Integration in Future Electronics Applications (DP), pp. 1126–1127.
DATE-2008-Dutt #design
Memory-aware NoC Exploration and Design (ND), pp. 1128–1129.
DATE-2008-XiongZV #incremental
Incremental Criticality and Yield Gradients (JX, VZ, CV), pp. 1130–1135.
DATE-2008-ShiRWP #analysis #modelling #statistics
Latch Modeling for Statistical Timing Analysis (SXS, AR, DW, DZP), pp. 1136–1141.
DATE-2008-MokhovY #configuration management #graph #partial order #synthesis
Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis (AM, AY), pp. 1142–1147.
DATE-2008-ThoguluvaRC #architecture #performance #programmable #security #using
Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor (JT, AR, STC), pp. 1148–1153.
DATE-2008-ChenDC #encryption #operating system
Operating System Controlled Processor-Memory Bus Encryption (XC, RPD, ANC), pp. 1154–1159.
DATE-2008-DasMJZMC #analysis #component #detection #implementation #network #performance
An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System (AD, SM, SJ, JZ, GM, ANC), pp. 1160–1165.
DATE-2008-PomeranzR #detection #fault #logic
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy (IP, SMR), pp. 1166–1171.
DATE-2008-LeeNKT #fault #generative
Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation (JL, SN, MK, MT), pp. 1172–1177.
DATE-2008-ShahidiG #multi #testing
Multi-Vector Tests: A Path to Perfect Error-Rate Testing (SS, SG), pp. 1178–1183.
DATE-2008-LiXHL #named #reduction #testing
iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing (JL, QX, YH, XL), pp. 1184–1189.
DATE-2008-ParkSP #embedded #execution #using
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors (SP, AS, YP), pp. 1190–1195.
DATE-2008-JonesBBCO #compilation #energy
Instruction Cache Energy Saving Through Compiler Way-Placement (TMJ, SB, BDB, JC, MFPO), pp. 1196–1201.
DATE-2008-XueSSQ #clustering #constraints #effectiveness #memory management #scheduling
Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints (CJX, EHMS, ZS, MQ), pp. 1202–1207.
DATE-2008-BeckRGC #configuration management #embedded
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications (ACSB, MBR, GG, LC), pp. 1208–1213.
DATE-2008-WolinskiK #automation #configuration management
Automatic Selection of Application-Specific Reconfigurable Processor Extensions (CW, KK), pp. 1214–1219.
DATE-2008-SahaSPBW #framework #implementation #message passing #parallel
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications (SS, JS, SP, SSB, WW), pp. 1220–1225.
DATE-2008-BrinksmaH #approach #dependence
Dependability for high-tech systems: an industry-as-laboratory approach (EB, JH), pp. 1226–1231.
DATE-2008-ChouM
User-Aware Dynamic Task Allocation in Networks-on-Chip (CLC, RM), pp. 1232–1237.
DATE-2008-FaruqueH #architecture #communication
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures (MAAF, JH), pp. 1238–1243.
DATE-2008-KwonHYMCE #communication
An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication (WCK, SMH, SY, BM, KMC, SKE), pp. 1244–1249.
DATE-2008-VermaBI #design #latency #paradigm
Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design (AKV, PB, PI), pp. 1250–1255.
DATE-2008-Parandeh-AfsharBI #integer #linear #programming #synthesis
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming (HPA, PB, PI), pp. 1256–1261.
DATE-2008-BonesanaPS #adaptation #regular expression
An adaptable FPGA-based System for Regular Expression Matching (IB, MP, MDS), pp. 1262–1267.
DATE-2008-VelevG #comparison #encoding #problem #satisfiability
Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems (MNV, PG), pp. 1268–1273.
DATE-2008-RealCCDV #analysis #hardware
Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis (DR, CC, JC, MD, FV), pp. 1274–1279.
DATE-2008-KulikowskiVWT
Power Balanced Gates Insensitive to Routing Capacitance Mismatch (KJK, VV, ZW, AT), pp. 1280–1285.
DATE-2008-DubrovaTT #analysis #feedback #on the #synthesis
On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers (ED, MT, HT), pp. 1286–1291.
DATE-2008-FanBSV #algebra #design #encryption
FPGA Design for Algebraic Tori-Based Public-Key Cryptography (JF, LB, KS, IV), pp. 1292–1297.
DATE-2008-KoN #automation #identification #validation
Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation (HFK, NN), pp. 1298–1303.
DATE-2008-ApostolakisGPP #functional #multi #self #symmetry
Functional Self-Testing for Bus-Based Symmetric Multiprocessors (AA, DG, MP, AMP), pp. 1304–1309.
DATE-2008-StrakaMBK #aspect-oriented #metric #quality
Theoretical and Practical Aspects of IDDQ Settling-Impact on Measurement Timing and Quality (BS, HARM, JB, SK), pp. 1310–1315.
DATE-2008-MatteisDB
Advanced Analog Filters for Telecommunications (MDM, SD, AB), pp. 1316–1321.
DATE-2008-GielenWMLMKGRN #challenge #reliability
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies (GGEG, PHNDW, EM, JL, JMM, BK, GG, RR, MN), pp. 1322–1327.
DATE-2008-GuiducciSGL #architecture #interface #novel
Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces (CG, AS, FKG, YL), pp. 1328–1333.
DATE-2008-ChattopadhyayCILAM #architecture #configuration management #modelling
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures (AC, XC, HI, RL, GA, HM), pp. 1334–1339.
DATE-2008-FarahaniFS #architecture #network #scalability #using
Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence (AFF, SMF, SS), pp. 1340–1345.
DATE-2008-MarconiLBG #algorithm #configuration management #online
Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems (TM, YL, KB, GG), pp. 1346–1351.
DATE-2008-DeleddaMVBGMKRHBCPLMCD #communication #configuration management #design #framework
Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor (AD, CM, AV, PB, AG, PM, MK, FR, MH, JB, MC, LP, RL, GM, FC, TD), pp. 1352–1357.
DATE-2008-MuirAL #automation #pipes and filters #streaming
Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications (MM, TA, IL), pp. 1358–1361.
DATE-2008-WolffPBC #analysis #detection #problem #towards
Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme (FGW, CAP, SB, RSC), pp. 1362–1365.
DATE-2008-YonedaF #functional #reuse #using
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects (TY, HF), pp. 1366–1369.
DATE-2008-HosseinabadyKMP #architecture #energy #graph #latency #performance #scalability
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs (MH, MRK, JM, DKP), pp. 1370–1373.
DATE-2008-BaiLD #adaptation #embedded
Adaptive Filesystem Compression for Embedded Systems (LSB, HL, RPD), pp. 1374–1377.
DATE-2008-FeinsteinTM #detection #equivalence #logic #using
Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits (DYF, MAT, DMM), pp. 1378–1381.
DATE-2008-LindgrenEAN #c #embedded #realtime
TinyTimber, Reactive Objects in C for Real-Time Embedded Systems (PL, JE, SA, JN), pp. 1382–1385.
DATE-2008-BriaoBW #realtime
Dynamic Task Allocation Strategies in MPSoC for Soft Real-time Applications (EWB, DB, FRW), pp. 1386–1389.
DATE-2008-NuzzoNSFP #design
Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications (PN, CN, SS, LF, GVdP), pp. 1390–1393.
DATE-2008-SammanHG #architecture #parallel #pipes and filters
Multicast Parallel Pipeline Router Architecture for Network-on-Chip (FAS, TH, MG), pp. 1396–1401.
DATE-2008-MedardoniLB #design #self
Variation tolerant NoC design by means of self-calibrating links (SM, ML, DB), pp. 1402–1407.
DATE-2008-Lotfi-KamranDLN #protocol
BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs (PLK, MD, CL, ZN), pp. 1408–1413.
DATE-2008-LoiAB #3d
Developing Mesochronous Synchronizers to Enable 3D NoCs (IL, FA, LB), pp. 1414–1419.
DATE-2008-VitkovskiKG #memory management #parallel
Memory Organization with Multi-Pattern Parallel Accesses (AV, GK, GG), pp. 1420–1425.
DATE-2008-KleanthousS #detection #named
CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches (MK, YS), pp. 1426–1431.
DATE-2008-KangK #design #framework #machine learning #manycore #named #optimisation #performance
Magellan: A Search and Machine Learning-based Framework for Fast Multi-core Design Space Exploration and Optimization (SK, RK), pp. 1432–1437.
DATE-2008-KM #design #process #queue
Process Variation Aware Issue Queue Design (RK, MM), pp. 1438–1443.
DATE-2008-MucciVMGDGKSCC #adaptation #array #configuration management #implementation #parallel #pipes and filters
Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array (CM, LV, IM, DG, AD, SG, JK, AS, LC, FC), pp. 1444–1449.
DATE-2008-ArteagaF #architecture #hardware #implementation #named #novel
GMDS: Hardware implementation of novel real output queuing architecture (RA, FT, REC, VdA, RS), pp. 1450–1455.
DATE-2008-BuboltzK #network
Front End Device for Content Networking (JB, TK), pp. 1456–1461.
DATE-2008-PurnaprajnaPP #configuration management #encryption #multi #power management
Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography (MP, CP, MP), pp. 1462–1467.
DATE-2008-ChoiC #testing #using
Digital bit stream jitter testing using jitter expansion (HWC, AC), pp. 1468–1473.
DATE-2008-PomeranzR08a #fault #taxonomy
A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution (IP, SMR), pp. 1474–1479.
DATE-2008-NeyGPVBG
A Design-for-Diagnosis Technique for SRAM Write Drivers (AN, PG, SP, AV, MB, VG), pp. 1480–1485.
DATE-2008-KeezerMD #injection #multi
Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications (DCK, DM, PD), pp. 1486–1491.
DATE-2008-HohenauerELAMBS #execution #optimisation
Retargetable Code Optimization for Predicated Execution (MH, FE, RL, GA, HM, GB, BS), pp. 1492–1497.
DATE-2008-EdwardsVT #compilation #concurrent #memory management #message passing #multi #programming #thread
Programming Shared Memory Multiprocessors with Deterministic Message-Passing Concurrency: Compiling SHIM to Pthreads (SAE, NV, OT), pp. 1498–1503.
DATE-2008-LublinermanT #code generation #composition #diagrams #reuse #usability
Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams (RL, ST), pp. 1504–1509.
DATE-2008-CruzBCM #embedded #modelling #named #realtime #synthesis
ezRealtime: A Domain-Specific Modeling Tool for Embedded Hard Real-Time Software Synthesis (FC, RSB, LCC, PRMM), pp. 1510–1515.
DATE-2008-BougardMBKC #3d #how #integration #topic
HOT TOPIC — 3D Integration or How to Scale in the 21st Century (BB, PM, LB, DKS, NC), p. 1516.

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