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Travelled to:
1 × USA
Collaborated with:
M.Tokoro M.Sato M.Ishigami E.Tamura H.Ohara
Talks about:
techniqu (1) system (1) compos (1) simul (1) modul (1) level (1) msi (1) lsi (1)

Person: Terunobu Ishimitsu

DBLP DBLP: Ishimitsu:Terunobu

Contributed to:

DAC 19781978

Wrote 1 papers:

DAC-1978-TokoroSITIO #simulation
A module level simulation technique for systems composed of LSI’s and MSI’s (MT, MS, MI, ET, TI, HO), pp. 418–427.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.