Stem lsi$ (all stems)

83 papers:

ICSME-2014-ParizyTK #design #fault #predict

Software Defect Prediction for LSI Designs (MP, KT, YK), pp. 565–568.

KDIR-2014-Bradford #ad hoc #query

Incorporating Ad Hoc Phrases in LSI Queries (RBB), pp. 61–70.

CSMR-2006-LormansD #design #question #requirements #traceability

Can LSI help Reconstructing Requirements Traceability in Design and Test? (ML, AvD), pp. 47–56.

ECIR-2006-ParaparB #identification #retrieval #topic

Sentence Retrieval with LSI and Topic Identification (DP, AB), pp. 119–130.

ECIR-2005-SkopalM #data access #metric #performance

Modified LSI Model for Efficient Search by Metric Access Methods (TS, PM), pp. 245–259.

DATE-2003-IwasakiNNNYONTOIE #multi #scalability

Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level (HI, JN, KN, KN, TY, MO, YN, YT, TO, MI, ME), pp. 20002–20007.

CIKM-2001-ZelikovitzH #classification #using

Using LSI for Text Classification in the Presence of Background Text (SZ, HH), pp. 113–118.

SIGIR-2001-AndoL #analysis

Iterative Residual Rescaling: An Analysis and Generalization of LSI (RKA, LL), pp. 154–162.

DATE-1999-IkedaKNSYMNO #architecture #scalability #video

An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture (MI, TK, KN, KS, TY, TM, JN, TO), p. 44–?.

DATE-1999-OchiaiINEO #embedded #framework #performance #video

High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit (KO, HI, JN, ME, TO), pp. 303–308.

DAC-1994-HaradaK #optimisation #performance

A Global Router Optimizing Timing and Area for High-Speed Bipolar LSI’s (IH, HK), pp. 177–181.

DAC-1993-MogakiSKH #approach #layout

Cooperative Approach to a Practical Analog LSI Layout System (MM, YS, MK, TH), pp. 544–549.

DAC-1991-MogakiKSY #constraints #layout

A Layout Improvement Method Based on Constraint Propagation for Analog LSI’s (MM, NK, NS, YY), pp. 510–513.

DAC-1987-OgiharaTM #design #named

ASTA: LSI Design Management System (TO, HT, SM), pp. 530–536.

DAC-1986-KishidaSIIH #logic

A delay test system for high speed logic LSI’s (KK, FS, YI, SI, TH), pp. 786–790.

DAC-1985-SakataK #comparison #linear

A circuit comparison system for bipolar linear LSI (TS, AK), pp. 429–434.

DAC-1984-AbadirR #case study #generative #testing

Test generation for LSI: A case study (MSA, HKR), pp. 180–195.

DAC-1984-AndersonP

UTMC’s LSI CAD system — highland (KA, RP), pp. 580–586.

DAC-1984-SchnurmannVP #automation #memory management #testing

An automated system for testing LSI memory chips (HDS, LJV, RMP), pp. 454–458.

DAC-1984-SuL #functional #testing

Functional testing techniques for digital LSI/VLSI systems (SYHS, TL), pp. 517–528.

DAC-1983-Jennings #automation

A topology for semicustom array-structured LSI devices, and their automatic customisation (PJ), pp. 675–681.

DAC-1983-OkazakiMY #multi

A multiple media delay simulator for MOS LSI circuits (KO, TM, TY), pp. 279–285.

DAC-1982-BoseKLNPW #fault

A fault simulator for MOS LSI circuits (AKB, PK, CYL, HNN, EPS, KWW), pp. 400–409.

DAC-1982-HirakawaSM #logic #simulation

Logic simulation for LSI (KH, NS, MM), pp. 755–761.

DAC-1982-HongYL

QCADS-a LSI CAD system for minicomputer (XLH, RkY, XlL), pp. 706–711.

DAC-1982-KambeCKION #algorithm #evaluation

A placement algorithm for polycell LSI and ITS evaluation (TK, TC, SK, TI, NO, IN), pp. 655–662.

DAC-1982-MatsudaFTMNKG #design #layout #low cost #named

LAMBDA: A quick, low cost layout design system for master-slice LSI s (TM, TF, KT, HM, HN, FK, SG), pp. 802–808.

DAC-1982-Monachino #design #scalability #verification

Design verification system for large-scale LSI designs (MM), pp. 83–90.

DAC-1982-Putatunda #automation #named

Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips (RP), pp. 616–621.

DAC-1982-SmithW #data transformation #design #low cost

A low cost, transportable, data management system for LSI/VLSI design (DCS, BSW), pp. 283–290.

DAC-1982-TakashimaMCY #source code #verification

Programs for verifying circuit connectivity of mos/lsi mask artwork (MT, TM, TC, KY), pp. 544–550.

DAC-1981-AgrawalSA #fault #quality

LSI product quality and fault coverage (VDA, SCS, PA), pp. 196–203.

DAC-1981-ArmstrongD #logic #named

GSP: A logic simulator for LSI (JRA, DED), pp. 518–524.

DAC-1981-BradyS #layout #optimisation #verification

Verification and optimization for LSI & PCB layout (HNB, RJSI), pp. 365–371.

DAC-1981-Bryant #named

MOSSIM: A switch-level simulator for MOS LSI (REB), pp. 786–790.

DAC-1981-Heller #design #physics

Contrasts in physical design between LSI and VLSI (WRH), pp. 676–683.

DAC-1981-HoltH #logic

A MOS/LSI oriented logic simulator (DH, DH), pp. 280–287.

DAC-1981-KhokhaniPFSH

Placement of variable size circuits on LSI masterslices (KHK, AMP, WF, JS, DH), pp. 426–434.

DAC-1981-MartinBLMMTW #design #named #problem

CELTIC — solving the problems of LSI design with an integrated polycell DA system (GM, JB, TL, DM, JM, DT, LW), pp. 804–811.

DAC-1981-PerskyES #automation #layout

The Hughes Automated Layout System — automated LSI/VLSI layout based on channel routing (GP, CE, DMS), pp. 22–28.

DAC-1981-Reitmeyer

CAD for military systems, an essential link to LSI, VLSI and VHSIC technology (RRJ), pp. 3–12.

DAC-1981-SatoNTSOY #layout #named

MILD — A cell-based layout system for MOS-LSI (KS, TN, MT, HS, MO, TY), pp. 828–836.

DAC-1980-NhamB #multi

A multiple delay simulator for MOS LSI circuits (HNN, AKB), pp. 610–617.

DAC-1980-SchnurmannP #interactive #testing

An interactive test data system for LSI production testing (HDS, RMP), pp. 362–366.

DAC-1980-ShiraishiH #performance #slicing

Efficient placement and routing techniques for master slice LSI (HS, FH), pp. 458–464.

DAC-1980-ShirakawaOHTO #layout #logic #random

A layout system for the random logic portion of MOS LSI (IS, NO, TH, ST, HO), pp. 92–99.

DAC-1980-SingletonC #automation #design #scalability

Practical automated design of LSI for large computers (JPS, NRC), pp. 556–559.

DAC-1979-AkinoSKN #simulation #verification

Circuit simulation and timing verification based on MOS/LSI mask information (TA, MS, YK, TN), pp. 88–94.

DAC-1979-BekeS #automation #interactive #layout #named

CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI (HB, WS), pp. 102–108.

DAC-1979-Chang #layout #recognition #using

LSI layout checking using bipolar device recognition technique (CSC), pp. 95–101.

DAC-1979-Goto #2d #algorithm #layout #problem #slicing

A two-dimensional placement algorithm for the master slice LSI layout problem (SG), pp. 11–17.

DAC-1979-IshiiYIS #diagrams #logic

An experimental input system of hand-drawn logic circuit diagram for LSI CAD (MI, MY, MI, HS), pp. 114–120.

DAC-1979-McCaw

Unified Shapes Checker — a checking tool for LSI (CRM), pp. 81–87.

DAC-1979-OhnoMS #logic #scalability #using #verification

Logic verification system for very large computers using LSI’s (YO, MM, KS), pp. 367–374.

DAC-1979-Rath

Hughes S&CG custom LSI layouts — “we did it our way” (RRR), pp. 392–397.

DAC-1979-WangB #automation

A software system for Automated Placement And Wiring of LSI chips (PTW, PB), pp. 327–329.

DAC-1979-Wilmore #database #design #interactive #layout #performance

The design of an efficient data base to support an interactive LSI layout system (JAW), pp. 445–451.

DAC-1978-AliaCMB #component #functional #modelling #simulation

LSI components modelling in a three-valued functional simulation (GA, PC, EM, FB), pp. 428–438.

DAC-1978-PreasG #automation #layout

Methods for hierarchical automatic layout of custom LSI circuit masks (BP, CWG), pp. 206–212.

DAC-1978-TokoroSITIO #simulation

A module level simulation technique for systems composed of LSI’s and MSI’s (MT, MS, MI, ET, TI, HO), pp. 418–427.

DAC-1977-AguleLRS #optimisation

An experimental system for power/timing optimization of LSI chips (BJA, JDL, AER, PKWS), pp. 147–152.

DAC-1977-Baird #algorithm #analysis #performance

Fast algorithms for LSI artwork analysis (HSB), pp. 303–311.

DAC-1977-CorreiaP

Introduction to an LSI test system (MC, FBP), pp. 460–461.

DAC-1977-CrockerMM #automation #design

Automatic ECL LSI design (NRC, RWM, AM), pp. 158–167.

DAC-1977-EichelbergerW #design #logic #testing

A logic design structure for LSI testability (EBE, TWW), pp. 462–468.

DAC-1977-HellerMD #predict #requirements

Prediction of wiring space requirements for LSI (WRH, WFM, WED), pp. 32–42.

DAC-1977-KhokhaniP #layout #problem

The chip layout problem: A placement procedure for lsi (KHK, AMP), pp. 291–297.

DAC-1976-DobesB #automation #design #geometry #recognition

The automatic recognition of silicon gate transistor geometries: An LSI design aid program (ID, RB), pp. 327–335.

DAC-1976-Feller #automation #layout #low cost

Automatic layout of low-cost quick-turnaround random-logic custom LSI devices (AF), pp. 79–85.

DAC-1976-IkemotoSIK

Correction and wiring check-system for master-slice LSI (YI, TS, KI, HK), pp. 336–343.

DAC-1976-KamikawaiKOYC

Placement and routing program for master-slice LSI’s (RK, KK, AO, IY, TC), pp. 245–250.

DAC-1976-PerskyDS #automation #design #named

LTX — a system for the directed automatic design of LSI circuits (GP, DND, DGS), pp. 399–407.

DAC-1976-Rozeboom #functional #problem #testing

Current problems related to LSI functional testing (RWR), pp. 203–204.

DAC-1975-Losleben #design #performance

Computer aided LSI circuit design: A relationship between topology and performance (PL), pp. 102–104.

DAC-1974-Huang #testing

MSI and LSI impact on digital systems testing (HHH), pp. 159–165.

DAC-1974-OzawaMS #design #slicing

Master slice LSI Computer Aided Design system (YO, MM, KS), pp. 19–25.

DAC-1974-Vaughn #array #functional #testing

Functional testing of LSI gate arrays (GDV), pp. 258–265.

DAC-1974-Wang #algorithm #clustering

A partitioning technique for LSI chips including a bunching algorithm (PTW), p. 91.

DAC-1973-PillingS #logic #predict

Computer-aided prediction of delays in LSI logic systems (DJP, HBS), pp. 182–186.

DAC-1972-Banes #design #fault

Error free MOS/LSI design system (AVB), pp. 29–33.

DAC-1972-Mattison #low cost #quality

A high quality, low cost router for MOS/LSI (RLM), pp. 94–103.

DAC-1971-LarsenM #clustering #equation #layout #logic

Partitioning and ordering of logic equations for optimum MOS LSI device layout (RPL, LM), pp. 131–142.

DAC-1969-Lewallen #design

Mos LSI computer aided design system (DRL), pp. 91–101.