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Travelled to:
1 × USA
Collaborated with:
G.Hung K.Gallivan R.A.Saleh
Talks about:
parallel (1) hierarch (1) circuit (1) simul (1) relax (1) use (1)

Person: Yen-Cheng Wen

DBLP DBLP: Wen:Yen=Cheng

Contributed to:

DAC 19901990

Wrote 1 papers:

DAC-1990-HungWGS #parallel #simulation #using
Parallel Circuit Simulation Using Hierarchical Relaxation (GGH, YCW, KG, RAS), pp. 394–399.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.