BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Used together with:
algorithm (2)
analysi (2)
yield (2)
maxim (1)
hors (1)

Stem circuitri$ (all stems)

7 papers:

DACDAC-2012-WeiLKP #benchmark #hardware #metric
Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry (SW, KL, FK, MP), pp. 90–95.
DATEDATE-2012-SharmaCAHCD #power management #variability
Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM (VS, SC, MA, JH, FC, WD), pp. 1042–1047.
DATEDATE-2010-Mirza-AghatabarBG #algorithm #pipes and filters
Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules (MMA, MAB, SKG), pp. 1249–1254.
DATEDATE-2007-DasM #analysis
Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry (TD, PRM), pp. 1277–1282.
ICPRICPR-1996-AleksandrovskyWGLG #algorithm #sequence
An algorithm derived from thalamocortical circuitry stores and retrieves temporal sequences (BA, JW, AG, GL, RG), pp. 550–554.
Retiming Synchronous Circuitry with Imprecise Delays (IK, RHJMO), pp. 322–326.
DACDAC-1993-PapaefthymiouR #named
TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry (MCP, KHR), pp. 497–502.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.