Stem masterslic$ (all stems)

5 papers:

DAC-1986-OgawaISTKYC #algorithm #optimisation #performance

Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs (YO, TI, YS, HT, TK, KY, KC), pp. 404–410.

DAC-1982-TeraiKSY #layout

A consideration of the number of horizontal grids used in the routing of a masterslice layout (MT, HK, KS, TY), pp. 121–128.

DAC-1981-KhokhaniPFSH

Placement of variable size circuits on LSI masterslices (KHK, AMP, WF, JS, DH), pp. 426–434.

DAC-1981-TanakaMNOTK #array #design #logic

An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2 (CT, SM, SN, TO, MT, KK), pp. 59–65.

DAC-1981-TanakaMTYOTKT #array #design #layout

An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3 (CT, SM, HT, TY, KO, MT, RK, MT), pp. 812–819.