Stem precharg$ (all stems)

3 papers:

DATE-2010-NassarBDDG #evaluation #named

BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation (MN, SB, JLD, GD, SG), pp. 849–854.

DAC-2000-SomasekharCRYD #analysis

Dynamic noise analysis in precharge-evaluate circuits (DS, SHC, KR, YY, VD), p. 243.

DAC-1990-McGeerB #analysis #network

Timing Analysis in Precharge/Unate Networks (PCM, RKB), pp. 124–129.