BibSLEIGH corpus
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Used together with:
use (2)
network (1)
remov (1)
function (1)
general (1)

Stem rewir$ (all stems)

6 papers:

DATEDATE-2014-LinWCH #logic
Rewiring for threshold logic circuit minimization (CCL, CYW, YCC, CYH), pp. 1–6.
DACDAC-2010-JoseHMH #robust
Rewiring for robustness (MJ, YH, RM, LH), pp. 469–474.
DACDAC-2010-YangLW #complexity #fault #named
ECR: a low complexity generalized error cancellation rewiring scheme (XY, TKL, YLW), pp. 511–516.
DATEDATE-2009-LinW #using
Rewiring using IRredundancy Removal and Addition (CCL, CYW), pp. 324–327.
ICMLICML-2007-GuoHFX #approach #modelling #network
Recovering temporally rewiring networks: a model-based approach (FG, SH, WF, EPX), pp. 321–328.
DACDAC-2000-ChangCSM #detection #functional #performance #symmetry #using
Fast post-placement rewiring using easily detectable functional symmetries (CWJC, CKC, PS, MMS), pp. 286–289.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.