BibSLEIGH corpus
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Used together with:
memori (5)
applic (3)
control (3)
time (3)
awar (3)

Stem sdram$ (all stems)

10 papers:

DATEDATE-2013-ShahKA #analysis #bound
Bounding SDRAM interference: detailed analysis vs. latency-rate analysis (HS, AK, BA), pp. 308–313.
DACDAC-2012-0001AG #memory management #realtime #runtime
Run-time power-down strategies for real-time SDRAM memory controllers (KC, BA, KG), pp. 988–993.
DATEDATE-2012-GoossensKAG #realtime
Memory-map selection for firm real-time SDRAM controllers (SG, TK, BA, KG), pp. 828–831.
DATEDATE-2012-ShahRK #bound #scheduling #using
Bounding WCET of applications using SDRAM with Priority Based Budget Scheduling in MPSoCs (HS, AR, AK), pp. 665–670.
DACDAC-2010-JangP #design #performance
Application-aware NoC design for efficient SDRAM access (WJ, DZP), pp. 453–456.
An SDRAM-aware router for Networks-on-Chip (WJ, DZP), pp. 800–805.
DACDAC-2005-HeitheckerE #requirements
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements (SH, RE), pp. 575–578.
DATEDATE-2003-MarchalGPBBCC #energy #memory management #multi
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms (PM, JIG, LP, DB, LB, FC, HC), pp. 10516–10523.
DACDAC-2002-JooCSLKC #energy #memory management #reduction
Energy exploration and reduction of SDRAM memory systems (YJ, YC, HS, HGL, KK, NC), pp. 892–897.
HPCAHPCA-2000-MathewMCD #design #memory management #parallel
Design of a Parallel Vector Access Unit for SDRAM Memory Systems (BKM, SAM, JBC, AD), pp. 39–48.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.