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Used together with:
verif (1)
fair (1)
system (1)

Stem transisiton$ (all stems)

1 papers:

CAVCAV-1996-KupfermanV96a #verification
Verification of Fair Transisiton Systems (OK, MYV), pp. 372–382.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.