MIXS: A mixed level simulator for large digital system logic verification
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Tohru Sasaki, Akihiko Yamada, Shunichi Kato, Terufumi Nakazawa, Kyoji Tomita, Nobuyoshi Nomizu
MIXS: A mixed level simulator for large digital system logic verification
DAC, 1980.

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@inproceedings{DAC-1980-SasakiYKNTN,
	author        = "Tohru Sasaki and Akihiko Yamada and Shunichi Kato and Terufumi Nakazawa and Kyoji Tomita and Nobuyoshi Nomizu",
	booktitle     = "{Proceedings of the 17th Design Automation Conference}",
	doi           = "10.1145/800139.804596",
	isbn          = "0-89791-020-6",
	pages         = "626--633",
	publisher     = "{ACM/IEEE}",
	title         = "{MIXS: A mixed level simulator for large digital system logic verification}",
	year          = 1980,
}

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