Irith Pomeranz, Sudhakar M. Reddy
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences
DAC, 1999.
@inproceedings{DAC-1999-PomeranzR, author = "Irith Pomeranz and Sudhakar M. Reddy", booktitle = "{Proceedings of the 36th Design Automation Conference}", doi = "10.1145/309847.310052", pages = "754--759", publisher = "{ACM Press}", title = "{Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences}", year = 1999, }