BibSLEIGH — Regularization of hierarchical VHDL-AMS models using bipartite graphs

Jochen Mades, Manfred Glesner
Regularization of hierarchical VHDL-AMS models using bipartite graphs
DAC, 2002.

DAC 2002

@inproceedings{DAC-2002-MadesG,
	author        = "Jochen Mades and Manfred Glesner",
	booktitle     = "{Proceedings of the 39th Design Automation Conference}",
	doi           = "10.1145/513918.514056",
	isbn          = "1-58113-461-4",
	pages         = "548--551",
	publisher     = "{ACM}",
	title         = "{Regularization of hierarchical VHDL-AMS models using bipartite graphs}",
	year          = 2002,
}

Jochen Mades, Manfred GlesnerRegularization of hierarchical VHDL-AMS models using bipartite graphsDAC, 2002.

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Jochen Mades, Manfred Glesner
Regularization of hierarchical VHDL-AMS models using bipartite graphs
DAC, 2002.