BibSLEIGH — Proceedings of the 39th Design Automation Conference

Proceedings of the 39th Design Automation Conference
DAC, 2002.

SYS

@proceedings{DAC-2002,
	acmid         = "513918",
	address       = "New Orleans, Louisiana, USA",
	isbn          = "1-58113-461-4",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 39th Design Automation Conference}",
	year          = 2002,
}

Contents (169 items)

DAC-2002-GavrielovGLSV: Wall street evaluates EDA (MG, RG, LL, VS, JV), p. 1.
DAC-2002-WirthlinM #delivery #using: IP delivery for FPGAs using Applets and JHDL (MJW, BM), pp. 2–7.
DAC-2002-MegerianDP #integer #linear #programming: Watermarking integer linear programming solutions (SM, MD, MP), pp. 8–13.
DAC-2002-BernardiS #design #library #using: Model design using hierarchical web-based libraries (FB, JFS), pp. 14–17.
DAC-2002-DrinicK #behaviour #synthesis: Behavioral synthesis via engineering change (MD, DK), pp. 18–21.
DAC-2002-NohlBSLMH #architecture #flexibility #performance #simulation: A universal technique for fast and flexible instruction-set architecture simulation (AN, GB, OS, RL, HM, AH), pp. 22–27.
DAC-2002-LyseckyCV #memory management #performance #profiling: A fast on-chip profiler memory (RLL, SC, FV), pp. 28–33.
DAC-2002-LekatsasHJ #design #embedded #hardware #performance: Design of an one-cycle decompression hardware for performance increase in embedded systems (HL, JH, VJ), pp. 34–39.
DAC-2002-SuBK #framework #reduction: A factorization-based framework for passivity-preserving model reduction of RLC systems (QS, VB, CKK), pp. 40–45.
DAC-2002-DanielP #distributed #order #reduction #strict: Model order reduction for strictly passive and causal distributed systems (LD, JRP), pp. 46–51.
DAC-2002-PhillipsDS #order #reduction: Guaranteed passive balancing transformations for model order reduction (JRP, LD, LMS), pp. 52–57.
DAC-2002-BaiVS #optimisation: Uncertainty-aware circuit optimization (XB, CV, PNS), pp. 58–63.
DAC-2002-SuHSN #network: Congestion-driven codesign of power and signal networks (HS, JH, SSS, SRN), pp. 64–69.
DAC-2002-KannanBB #estimation #metric #on the: On metrics for comparing routability estimation methods for FPGAs (PK, SB, DB), pp. 70–75.
DAC-2002-KahngCGLNRH #question #tool support: Tools or users: which is the bigger bottleneck? (ABK, RC, PG, LL, NN, PKR, LvdH), pp. 76–77.
DAC-2002-SeryBD #question #why: Life is CMOS: why chase the life after? (GS, SB, VD), pp. 78–83.
DAC-2002-Pogge #challenge #effectiveness: The next chip challenge: effective methods for viable mixed technology SoCs (HBP), pp. 84–87.
DAC-2002-IonescuDMBG #hybrid #towards: Few electron devices: towards hybrid CMOS-SET integrated circuits (AMI, MJD, SM, KB, JG), pp. 88–93.
DAC-2002-MartelDAWA #logic: Carbon nanotube field-effect transistors and logic circuits (RM, VD, JA, SJW, PA), pp. 94–98.
DAC-2002-BertaccoO #performance #representation #simulation: Efficient state representation for symbolic simulation (VB, KO), pp. 99–104.
DAC-2002-KolblKAD #simulation: Handling special constructs in symbolic simulation (AK, JHK, KA, RFD), pp. 105–110.
DAC-2002-HazelhurstWKF #approach #design #hybrid #verification: A hybrid verification approach: getting deep into the design (SH, OW, GK, LF), pp. 111–116.
DAC-2002-CabodiCQ #bound #model checking #question #satisfiability: Can BDDs compete with SAT solvers on bounded model checking? (GC, PC, SQ), pp. 117–122.
DAC-2002-SemeriaMPESN #concurrent #design #multi #thread #verification: RTL c-based methodology for designing and verifying a multi-threaded processor (LS, RM, BMP, AE, AS, DN), pp. 123–128.
DAC-2002-OliveiraH #automation #generative #interface #monitoring #specification: High-Level specification and automatic generation of IP interface monitors (MTO, AJH), pp. 129–134.
DAC-2002-EderB #logic #performance #pipes and filters #verification: Achieving maximum performance: a method for the verification of interlocked pipeline control logic (KE, GB), pp. 135–140.
DAC-2002-ChakrabartiDCB #interface #realtime #specification #verification: Formal verification of module interfaces against real time specifications (AC, PD, PPC, AB), pp. 141–145.
DAC-2002-DagaMSWW #automation #generative: Automated timing model generation (AJD, LM, SS, CW, QW), pp. 146–151.
DAC-2002-MoonKB #graph #reduction: Timing model extraction of hierarchical blocks by graph reduction (CWM, HK, KPB), pp. 152–157.
DAC-2002-FoltinFT #abstraction #concept #independence #modelling #performance: Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency (MF, BF, ST), pp. 158–163.
DAC-2002-Higuchi #detection #multi #scalability: An implication-based method to detect multi-cycle paths in large sequential circuits (HH), pp. 164–169.
DAC-2002-ParkMJ #framework #information management #mobile #personalisation #smarttech: The wearable motherboard: a framework for personalized mobile information processing (PMIP) (SP, KM, SJ), pp. 170–174.
DAC-2002-MarculescuMK #challenge #modelling #optimisation: Challenges and opportunities in electronic textiles modeling and optimization (DM, RM, PKK), pp. 175–180.
DAC-2002-BrunoliHJKMM #question: Analog intellectual property: now? Or never? (MB, MH, FJ, RK, RM, AJM), pp. 181–182.
DAC-2002-ZhangHC #energy #scheduling: Task scheduling and voltage selection for energy minimization (YZ, XH, DZC), pp. 183–188.
DAC-2002-RakhmatovVC #scalability: Battery-conscious task sequencing for portable devices including voltage/clock scaling (DNR, SBKV, CC), pp. 189–194.
DAC-2002-KadayifKK #adaptation #energy #parallel: An energy saving strategy based on adaptive loop parallelization (IK, MTK, MK), pp. 195–200.
DAC-2002-MoB: River PLAs: a regular circuit structure (FM, RKB), pp. 201–206.
DAC-2002-UmK #synthesis: Layout-aware synthesis of arithmetic circuits (JU, TK), pp. 207–212.
DAC-2002-LuzKK #automation #energy #memory management #migration #multi: Automatic data migration for reducing energy consumption in multi-bank memory systems (VDLL, MTK, IK), pp. 213–218.
DAC-2002-KandemirRC #embedded #memory management #multi: Exploiting shared scratch pad memory space in embedded multiprocessor systems (MTK, JR, ANC), pp. 219–224.
DAC-2002-ChoiK #code generation #scheduling: Address assignment combined with scheduling in DSP code generation (YC, TK), pp. 225–230.
DAC-2002-Sargent #agile #integration #internet #multi: Multifunctional photonic integration for the agile optical internet (EHS), pp. 231–234.
DAC-2002-MaloneyBM #design: Computer aided design of long-haul optical transmission systems (JGM, BEB, CRM), p. 235.
DAC-2002-KurzwegLMKC #modelling #performance: A fast optical propagation technique for modeling micro-optical systems (TPK, SPL, JAM, MK, DMC), pp. 236–241.
DAC-2002-BrodersenHKKLK #design #question #what: Nanometer design: what hurts next...? (RWB, AMH, JK, DK, MAL, MK), p. 242.
DAC-2002-AbramoviciYR #low cost: Low-cost sequential ATPG with clock-control DFT (MA, XY, EMR), pp. 243–248.
DAC-2002-WohlWPM #effectiveness: Effective diagnostics through interval unloads in a BIST environment (PW, JAW, SP, GAM), pp. 249–254.
DAC-2002-PomeranzKR #on the: On output response compression in the presence of unknown output values (IP, SK, SMR), pp. 255–258.
DAC-2002-ChenD: Software-based diagnosis for processors (LC, SD), pp. 259–262.
DAC-2002-LiuP #design #power management: Design of a high-throughput low-power IS95 Viterbi decoder (XL, MCP), pp. 263–268.
DAC-2002-RaganSS #co-evolution #concurrent #cost analysis #design #hardware: A detailed cost model for concurrent use with hardware/software co-design (DR, PS, PS), pp. 269–274.
DAC-2002-OhH #data flow #graph #multi #performance #synthesis: Efficient code synthesis from extended dataflow graphs for multimedia applications (HO, SH), pp. 275–280.
DAC-2002-SanderJ #communication #design #refinement: Transformation based communication and clock domain refinement for system design (IS, AJ), pp. 281–286.
DAC-2002-RichterZJE #analysis #composition #design #framework #platform #scheduling: Model composition for scheduling analysis in platform design (KR, DZ, MJ, RE), pp. 287–292.
DAC-2002-LeeP #analysis #design #embedded #performance #simulation: Timed compiled-code simulation of embedded software for performance analysis of SOC design (JYL, ICP), pp. 293–298.
DAC-2002-JollyPM #automation #equivalence: Automated equivalence checking of switch level circuits (SJ, ANP, TM), pp. 299–304.
DAC-2002-AnastasakisDMS #performance: A practical and efficient method for compare-point matching (DA, RFD, HKTM, TS), pp. 305–310.
DAC-2002-ChangC #implementation #self #verification: Self-referential verification of gate-level implementations of arithmetic circuits (YTC, KTC), pp. 311–316.
DAC-2002-SantariniJMEKRRY #question: Whither (or wither?) ASIC handoff? (MS, SJ, MM, TE, SK, KNR, TR, KY), pp. 317–318.
DAC-2002-JiangB #logic #simulation #specification #synthesis #using: Software synthesis from synchronous specifications using logic simulation techniques (YJ, RKB), pp. 319–324.
DAC-2002-PeymandoustMS #algebra #embedded #library #using: Complex library mapping for embedded software using symbolic algebra (AP, GDM, TS), pp. 325–330.
DAC-2002-AbbaspourZ: Retargetable binary utilities (MA, JZ), pp. 331–336.
DAC-2002-HuangM #configuration management #parallel: Exploiting operation level parallelism through dynamically reconfigurable datapaths (ZH, SM), pp. 337–342.
DAC-2002-HortaLTP #configuration management #hardware #plugin #runtime: Dynamic hardware plugins in an FPGA with partial run-time reconfiguration (ELH, JWL, DET, DBP), pp. 343–348.
DAC-2002-ChenMB #configuration management #generative: A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator (JC, JM, KB), pp. 349–354.
DAC-2002-KrsticLCCD #design #embedded #self: Embedded software-based self-testing for SoC design (AK, WCL, KTC, LC, SD), pp. 355–360.
DAC-2002-BhuniaRS #analysis #detection #fault #locality #novel: A novel wavelet transform based transient current analysis for fault detection and localization (SB, KR, JS), pp. 361–366.
DAC-2002-AttarhaN #analysis #fault #modelling #using: Signal integrity fault analysis using reduced-order modeling (AA, MN), pp. 367–370.
DAC-2002-LiouWCDMKW #fault #multi #performance #testing #using: Enhancing test efficiency for delay fault testing using multiple-clocked schemes (JJL, LCW, KTC, JD, MRM, RK, TWW), pp. 371–374.
DAC-2002-Berthet #design #industrial #mobile #multi: Going mobile: the next horizon for multi-million gate designs in the semi-conductor industry (CB), pp. 375–378.
DAC-2002-CaoLCC #delivery #megamodelling #named #power management: HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery (YC, YML, THC, CCPC), pp. 379–384.
DAC-2002-BodapatiN #analysis #megamodelling: High-level current macro-model for power-grid analysis (SB, FNN), pp. 385–390.
DAC-2002-AmickGL #concept #interface #megamodelling: Macro-modeling concepts for the chip electrical interface (BWA, CRG, DL), pp. 391–394.
DAC-2002-ZhengP #analysis #modelling #network #symmetry: Modeling and analysis of regular symmetrically structured power/ground distribution networks (HZ, LTP), pp. 395–398.
DAC-2002-BadarogluTDWMVG #optimisation #reduction #using: Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients (MB, KT, SD, PW, HDM, IV, GGEG), pp. 399–404.
DAC-2002-ChelceaN #optimisation #scalability: Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems (TC, SMN), pp. 405–410.
DAC-2002-KondratyevL #design #tool support: Design of asynchronous circuits by synchronous CAD tools (AK, KL), pp. 411–414.
DAC-2002-Sotiriou #implementation #using: Implementing asynchronous circuits using a conventional EDA tool-flow (CPS), pp. 415–418.
DAC-2002-IwamaKY #design #quantum: Transformation rules for designing CNOT-based quantum circuits (KI, YK, SY), pp. 419–424.
DAC-2002-BernasconiCLP #logic #performance #symmetry: Fast three-level logic minimization based on autosymmetry (AB, VC, FL, LP), pp. 425–430.
DAC-2002-DaemsGS #modelling #performance: An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits (WD, GGEG, WMCS), pp. 431–436.
DAC-2002-LiuSRC #data mining #design #megamodelling #mining #scalability: Remembrance of circuits past: macromodeling by data mining in large analog design spaces (HL, AS, RAR, LRC), pp. 437–442.
DAC-2002-BajdechiHG #design: Optimal design of delta-sigma ADCs by design space exploration (OB, JHH, GGEG), pp. 443–448.
DAC-2002-VandenbusscheULSG #design: Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter (JV, KU, EL, MS, GGEG), pp. 449–454.
DAC-2002-MurugavelR #estimation #modelling #petri net: Petri net modeling of gate and interconnect delays for power estimation (AKM, NR), pp. 455–460.
DAC-2002-KapurCS #estimation #novel #optimisation #reduction #using: Power estimation in global interconnects and its reduction using a novel repeater optimization methodology (PK, GC, KS), pp. 461–466.
DAC-2002-JungKK #logic: Low-swing clock domino logic incorporating dual supply and dual threshold voltages (SOJ, KWK, SMK), pp. 467–472.
DAC-2002-AgarwalLR #named #power management: DRG-cache: a data retention gated-ground cache for low power (AA, HL, KR), pp. 473–478.
DAC-2002-SmithNMCFKMB #embedded #question #tool support: Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant? (GS, DN, SM, RC, JF, KK, GM, BB), p. 479.
DAC-2002-AnisMEA #automation #clustering #performance #power management #reduction #using: Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique (MA, MM, MIE, SA), pp. 480–485.
DAC-2002-KarnikYTWBGDB #optimisation #performance: Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors (TK, YY, JT, LW, SMB, VG, VD, SB), pp. 486–491.
DAC-2002-KangSC #power management #synthesis: An optimal voltage synthesis technique for a power-efficient satellite application (DIK, JS, SPC), pp. 492–497.
DAC-2002-Perrott #behaviour #performance #simulation: Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits (MHP), pp. 498–503.
DAC-2002-YangP #component #multi #simulation #using: Time-domain steady-state simulation of frequency-dependent components using multi-interval Chebyshev method (BY, JRP), pp. 504–509.
DAC-2002-Roychowdhury: A time-domain RF steady-state method for closely spaced tones (JSR), pp. 510–513.
DAC-2002-Casinovi #algorithm #analysis: An algorithm for frequency-domain noise analysis in nonlinear systems (GC), pp. 514–517.
DAC-2002-Ykman-CouvreurLVCNK #memory management #network #optimisation #performance: System-level performance optimization of the data queueing memory management in high-speed network processors (CYC, JL, DV, FC, AN, GEK), pp. 518–523.
DAC-2002-YeMB #analysis #network #power management: Analysis of power consumption on switch fabrics in network routers (TTY, GDM, LB), pp. 524–529.
DAC-2002-WhelihanS #memory management #network #optimisation: Memory optimization in single chip network switch fabrics (DW, HS), pp. 530–535.
DAC-2002-VanasscheGS #behaviour #modelling: Behavioral modeling of (coupled) harmonic oscillators (PV, GGEG, WMCS), pp. 536–541.
DAC-2002-HartongHB #algorithm #model checking #verification: Model checking algorithms for analog verification (WH, LH, EB), pp. 542–547.
DAC-2002-MadesG #graph #modelling #using: Regularization of hierarchical VHDL-AMS models using bipartite graphs (JM, MG), pp. 548–551.
DAC-2002-MassoudW #approach: Improving the generality of the fictitious magnetic charge approach to computing inductances in the presence of permeable materials (YM, JW), pp. 552–555.
DAC-2002-OrshanskyK #analysis #framework #probability: A general probabilistic framework for worst case timing analysis (MO, KK), pp. 556–561.
DAC-2002-ZengAA #identification #using: False timing path identification using ATPG techniques and delay-based information (JZ, MSA, JAA), pp. 562–565.
DAC-2002-LiouKWC #analysis #performance #statistics #testing #validation: False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation (JJL, AK, LCW, KTC), pp. 566–569.
DAC-2002-CadambiMA #functional #hardware #performance #scalability #simulation: A fast, inexpensive and scalable hardware acceleration technique for functional simulation (SC, CM, PA), pp. 570–575.
DAC-2002-DillJRBFFRSW #verification: Formal verification methods: getting around the brick wall (DLD, NJ, SR, GB, LF, HF, RKR, GS, CW), pp. 576–577.
DAC-2002-HrkicL #named #synthesis: S-Tree: a technique for buffered routing tree synthesis (MH, JL), pp. 578–583.
DAC-2002-XiangWT #algorithm: An algorithm for integrated pin assignment and buffer planning (HX, DFW, XT), pp. 584–589.
DAC-2002-ShenoyN #database #performance: An efficient routing database (NVS, WN), pp. 590–595.
DAC-2002-GharsalliMRJ #automation #embedded #generative #memory management #multi: Automatic generation of embedded memory wrapper for multiprocessor SoC (FG, SM, FR, AAJ), pp. 596–601.
DAC-2002-SiegmundM #communication #declarative #hardware #novel #protocol #specification #synthesis: A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications (RS, DM), pp. 602–607.
DAC-2002-SeoKP #algorithm #memory management #synthesis: An integrated algorithm for memory allocation and assignment in high-level synthesis (JS, TK, PRP), pp. 608–611.
DAC-2002-MolinaMH #multi #synthesis: High-level synthesis of multiple-precision circuitsindependent of data-objects length (MCM, JMM, RH), pp. 612–615.
DAC-2002-ChakrabortyEKT #embedded #realtime #scheduling: Schedulability of event-driven code blocks in real-time embedded systems (SC, TE, SK, LT), pp. 616–621.
DAC-2002-WolfSE #analysis #formal method: Associative caches in formal software timing analysis (FW, JS, RE), pp. 622–627.
DAC-2002-KandemirC #design #memory management: Compiler-directed scratch pad memory hierarchy design and management (MTK, ANC), pp. 628–633.
DAC-2002-SchaumontKV #design: Unlocking the design secrets of a 2.29 Gb/s Rijndael processor (PS, HK, IV), pp. 634–639.
DAC-2002-RichardsonHHZSL #cpu: The iCOREtm 520 MHz synthesizable CPU core (NR, LBH, RH, TZ, NS, JL), pp. 640–645.
DAC-2002-MemikM #flexibility #network: A flexible accelerator for layer 7 networking applications (GM, WHMS), pp. 646–651.
DAC-2002-RabaeyKBCSLH #question #what: What’s the next EDA driver? (JMR, JK, DB, RC, DS, LL, RH), p. 652.
DAC-2002-VrudhulaBS #estimation: Estimation of the likelihood of capacitive coupling noise (SBKV, DB, SS), pp. 653–658.
DAC-2002-MortonD #estimation: Crosstalk noise estimation for noise management (PBM, WWMD), pp. 659–664.
DAC-2002-KrauterW #analysis: Variable frequency crosstalk noise analysis: : a methodology to guarantee functionality from dc to fmax (BK, DW), pp. 665–668.
DAC-2002-MaH #constraints #towards: Towards global routing with RLC crosstalk constraints (JDZM, LH), pp. 669–672.
DAC-2002-ChandraC #reduction #testing #using: Reduction of SOC test data volume, scan power and testing time using alternating run-length codes (AC, KC), pp. 673–678.
DAC-2002-KayCM #embedded: Embedded test control schemes for compression in SOCs (DK, SC, SM), pp. 679–684.
DAC-2002-IyengarCM #constraints #reduction #scheduling: Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs (VI, KC, EJM), pp. 685–690.
DAC-2002-LahiriDR #architecture #communication #design #performance #power management: Communication architecture based power management for battery efficient system design (KL, SD, AR), pp. 691–696.
DAC-2002-DelaluzSKVI #energy: Scheduler-based DRAM energy management (VD, AS, MTK, NV, MJI), pp. 697–702.
DAC-2002-KadayifKS #approach #integer #linear #multi #programming: An integer linear programming based approach for parallelizing applications in On-chip multiprocessors (IK, MTK, US), pp. 703–708.
DAC-2002-Zorian #framework: Embedding infrastructure IP for SOC yield improvement (YZ), pp. 709–712.
DAC-2002-AbramoviciSE #embedded #using: Using embedded FPGAs for SoC yield improvement (MA, CES, ME), pp. 713–724.
DAC-2002-AnderssonBCH #approach #automation #design #problem #proving: A proof engine approach to solving combinational design automation problems (GA, PB, BC, ZH), pp. 725–730.
DAC-2002-AloulRMS #satisfiability #symmetry: Solving difficult SAT instances in the presence of symmetry (FAA, AR, ILM, KAS), pp. 731–736.
DAC-2002-AloulSS #how #named #question: Satometer: how much have we searched? (FAA, BDS, KAS), pp. 737–742.
DAC-2002-PilarskiH #satisfiability: SAT with partial clauses and back-leaps (SP, GH), pp. 743–746.
DAC-2002-GanaiAGZM #algorithm #satisfiability: Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver (MKG, PA, AG, LZ, SM), pp. 747–750.
DAC-2002-MahawarSS #performance: A solenoidal basis method for efficient inductance extraction (HM, VS, WS), pp. 751–756.
DAC-2002-LinBP #2d #modelling #on the: On the efficacy of simplified 2D on-chip inductance models (TL, MWB, LTP), pp. 757–762.
DAC-2002-VenkatesanDM #distributed #physics: A physical model for the transient response of capacitively loaded distributed rlc interconnects (RV, JAD, JDM), pp. 763–766.
DAC-2002-KoukabDD #analysis #named #performance: HSpeedEx: a high-speed extractor for substrate noise analysis in complex mixed signal SOC (AK, CD, MJD), pp. 767–770.
DAC-2002-SchrikM #modelling: Combined BEM/FEM substrate resistance modeling (ES, NPvdM), pp. 771–776.
DAC-2002-RaviRPS #design #framework #platform #security: System design methodologies for a wireless security processing platform (SR, AR, NRP, MS), pp. 777–782.
DAC-2002-PintoCS #communication #constraints #synthesis: Constraint-driven communication synthesis (AP, LPC, ALSV), pp. 783–788.
DAC-2002-CesarioBGLNPYJD #approach #component #design #manycore: Component-based design approach for multicore SoCs (WOC, AB, LG, DL, GN, YP, SY, AAJ, MDN), pp. 789–794.
DAC-2002-VaratkarM #analysis #design #multi #network: Traffic analysis for on-chip networks design of multimedia applications (GV, RM), pp. 795–800.
DAC-2002-ShimizuD #generative #metric #simulation #specification: Deriving a simulation input generator and a coverage metric from a formal specification (KS, DLD), pp. 801–806.
DAC-2002-LachishMUZ #analysis #functional: Hole analysis for functional coverage data (OL, EM, SU, AZ), pp. 807–812.
DAC-2002-ShengTH #effectiveness #safety #using: Effective safety property checking using simulation-based sequential ATPG (SS, KT, MSH), pp. 813–818.
DAC-2002-BartleyGB #comparison #pseudo #random testing #testing #verification: A comparison of three verification techniques: directed testing, pseudo-random testing and property checking (MB, DG, TB), pp. 819–823.
DAC-2002-ChiasseriniNS #communication #energy #protocol: Energy-efficient communication protocols (CFC, PN, VS), pp. 824–829.
DAC-2002-Shanbhag #energy #reliability: Reliable and energy-efficient digital signal processing (NRS), pp. 830–835.
DAC-2002-SteyaertV #named #paradigm #power management #question: CMOS: a paradigm for low power wireless? (MS, PJV), pp. 836–841.
DAC-2002-LinC #named #orthogonal: TCG-S: orthogonal coupling of P*-admissible representations for general floorplans (JML, YWC), pp. 842–847.
DAC-2002-TangW #constraints #performance: Floorplanning with alignment and performance constraints (XT, DFW), pp. 848–853.
DAC-2002-ZhongD #algorithm #constraints #multi #optimisation: Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control (KZ, SD), pp. 854–859.
DAC-2002-ChenMB02a: Coping with buffer delay change due to power and ground noise (LHC, MMS, FB), pp. 860–865.
DAC-2002-Sheehan #predict: Osculating Thevenin model for predicting delay and slew of capacitively characterized cells (BNS), pp. 866–869.
DAC-2002-ChoiRD #generative: Timed pattern generation for noise-on-delay calculation (SHC, KR, FD), pp. 870–873.
DAC-2002-LeeKK #named #verification: VeriCDF: a new verification methodology for charged device failures (JL, KWK, SMK), pp. 874–879.
DAC-2002-ThieleCGK #architecture #design #framework #trade-off: A framework for evaluating design tradeoffs in packet processing architectures (LT, SC, MG, SK), pp. 880–885.
DAC-2002-BonaSSZSZ #clustering #embedded #energy #estimation #optimisation: Energy estimation and optimization of embedded VLIW processors based on instruction clustering (AB, MS, DS, VZ, CS, RZ), pp. 886–891.
DAC-2002-JooCSLKC #energy #memory management #reduction: Energy exploration and reduction of SDRAM memory systems (YJ, YC, HS, HGL, KK, NC), pp. 892–897.
DAC-2002-GuptaSDGNKKR #coordination #performance #synthesis: Coordinated transformations for high-level synthesis of high performance microprocessor blocks (SG, NS, NDD, RKG, AN, TK, MK, SR), pp. 898–903.
DAC-2002-WongMP #concept #synthesis: Forward-looking objective functions: concept & applications in high level synthesis (JLW, SM, MP), pp. 904–909.
DAC-2002-KoushanfarWFP: ILP-based engineering change (FK, JLW, JF, MP), pp. 910–915.

Proceedings of the 39th Design Automation ConferenceDAC, 2002.

Contents (169 items)

Proceedings of the 39th Design Automation Conference
DAC, 2002.