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Travelled to:
1 × USA
Collaborated with:
M.Glesner
Talks about:
hierarch (1) bipartit (1) regular (1) model (1) graph (1) vhdl (1) use (1)

Person: Jochen Mades

DBLP DBLP: Mades:Jochen

Contributed to:

DAC 20022002

Wrote 1 papers:

DAC-2002-MadesG #graph #modelling #using
Regularization of hierarchical VHDL-AMS models using bipartite graphs (JM, MG), pp. 548–551.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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